From 466e73b19b34a1500303faffc4b17d849438fad0 Mon Sep 17 00:00:00 2001 From: Macpaul Lin <macpaul@andestech.com> Date: Mon, 24 Oct 2011 16:48:39 +0800 Subject: [PATCH] nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment Add ARCH_DMA_MINALIGN definition to asm/cache.h Signed-off-by: Macpaul Lin <macpaul@andestech.com> --- arch/nds32/include/asm/cache.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index d769196213..fc22c7bc05 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG); #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* + * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. + * We use that value for aligning DMA buffers unless the board config has + * specified an alternate cache line size. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 32 +#endif + #endif /* _ASM_CACHE_H */ -- 2.39.5