From 12cc44884b0e74260c2f7396b993f178f8c8df27 Mon Sep 17 00:00:00 2001
From: Chee Hong Ang <chee.hong.ang@intel.com>
Date: Fri, 10 Jul 2020 23:53:13 +0800
Subject: [PATCH] arm: socfpga: soc64: Initialize timer in SPL only
Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/timer_s10.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c
index 3ad98bdb25..7d5598e1a3 100644
--- a/arch/arm/mach-socfpga/timer_s10.c
+++ b/arch/arm/mach-socfpga/timer_s10.c
@@ -14,6 +14,7 @@
*/
int timer_init(void)
{
+#ifdef CONFIG_SPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
@@ -22,6 +23,6 @@ int timer_init(void)
/* enable processor pysical counter */
asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable));
asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval));
-
+#endif
return 0;
}
--
2.39.5