From: Stephen Warren <swarren@nvidia.com> Date: Mon, 4 Mar 2013 13:29:40 +0000 (+0000) Subject: ARM: implement erratum 716044 workaround X-Git-Tag: v2025.01-rc5-pxa1908~16341^2~8 X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-logo.png?a=commitdiff_plain;h=c5d4752c0541ea0af559250bd2bec6556fed6915;p=u-boot.git ARM: implement erratum 716044 workaround Add common code to enable the workaround for ARM erratum 716044. This will be enabled for Tegra. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- diff --git a/README b/README index 7f2506a9b9..616bfb0c6e 100644 --- a/README +++ b/README @@ -485,6 +485,7 @@ The following options need to be configured: Thumb2 this flag will result in Thumb2 code generated by GCC. + CONFIG_ARM_ERRATA_716044 CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index fa5fad1b0c..c0e184994a 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -310,6 +310,12 @@ ENTRY(cpu_init_cp15) #endif mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_ARM_ERRATA_716044 + mrc p15, 0, r0, c1, c0, 0 @ read system control register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c1, c0, 0 @ write system control register +#endif + #ifdef CONFIG_ARM_ERRATA_742230 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4