From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 20 Jul 2018 08:16:21 +0000 (+0200)
Subject: arm: zynq: Remove fclk-enable property for cse-nor target
X-Git-Tag: v2025.01-rc5-pxa1908~3800^2~16
X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-logo.png?a=commitdiff_plain;h=7996fcca9d401437527d9e9a464cb79965c90c98;p=u-boot.git
arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts
index ba6f9a1a79..edc8f59f6c 100644
--- a/arch/arm/dts/zynq-cse-nor.dts
+++ b/arch/arm/dts/zynq-cse-nor.dts
@@ -56,7 +56,6 @@
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
- fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll",
"iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x",