From: Bin Meng <bmeng.cn@gmail.com>
Date: Thu, 10 Sep 2015 06:20:28 +0000 (-0700)
Subject: x86: galileo: Add PCIe root port IRQ routing
X-Git-Tag: v2025.01-rc5-pxa1908~11659^2~3
X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-logo.png?a=commitdiff_plain;h=5bf0f7f65d40447cec0f3d91abda59eb4a4f88af;p=u-boot.git

x86: galileo: Add PCIe root port IRQ routing

Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f119bf7f42..a4e16760d5 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -92,6 +92,18 @@
 				PCI_BDF(0, 21, 0) INTA PIRQE
 				PCI_BDF(0, 21, 1) INTB PIRQF
 				PCI_BDF(0, 21, 2) INTC PIRQG
+				PCI_BDF(0, 23, 0) INTA PIRQA
+				PCI_BDF(0, 23, 1) INTB PIRQB
+
+				/* PCIe root ports downstream interrupts */
+				PCI_BDF(1, 0, 0) INTA PIRQA
+				PCI_BDF(1, 0, 0) INTB PIRQB
+				PCI_BDF(1, 0, 0) INTC PIRQC
+				PCI_BDF(1, 0, 0) INTD PIRQD
+				PCI_BDF(2, 0, 0) INTA PIRQB
+				PCI_BDF(2, 0, 0) INTB PIRQC
+				PCI_BDF(2, 0, 0) INTC PIRQD
+				PCI_BDF(2, 0, 0) INTD PIRQA
 			>;
 		};
 	};