From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Sun, 5 May 2013 16:11:59 +0000 (+0000)
Subject: mxs: Explain why some mx23 DDR registers are not configured
X-Git-Tag: v2025.01-rc5-pxa1908~16266^2~7
X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-logo.png?a=commitdiff_plain;h=286a88cf34bcfec4a1051b5ee3553277e6c31e2e;p=u-boot.git

mxs: Explain why some mx23 DDR registers are not configured

Put an explanation in the source code as to why some DDR registers do not
need to be configured.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index 4ed197b51d..3902406441 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -127,6 +127,15 @@ static void initialize_dram_values(void)
 
 	mxs_adjust_memory_params(dram_vals);
 
+	/*
+	 * HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
+	 * per FSL bootlets code.
+	 *
+	 * mx23 Reference Manual marks HW_DRAM_CTL27 and HW_DRAM_CTL28 as
+	 * "reserved".
+	 * HW_DRAM_CTL8 is setup as the last element.
+	 * So skip the initialization of these HW_DRAM_CTL registers.
+	 */
 	for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
 		if (i == 8 || i == 27 || i == 28 || i == 35)
 			continue;