]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
mtd: spi-nor-id: Add S25FS064S, S25FS128S, S25FS256S IDs
authorTakahiro Kuwano <Takahiro.Kuwano@infineon.com>
Fri, 27 Sep 2024 01:11:19 +0000 (10:11 +0900)
committerTom Rini <trini@konsulko.com>
Thu, 10 Oct 2024 14:12:13 +0000 (08:12 -0600)
The S25FS064S, S25FS128S, and S25FS256S are the same family of SPI NOR
Flash devices with S25FS512S. Some difference depending on the device
densities are taken care in post SFDP fixup.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Pratyush Yadav <pratyush@kernel.org>
drivers/mtd/spi/spi-nor-core.c
drivers/mtd/spi/spi-nor-ids.c

index b633f3092b1f48816d664493a19042d86eec708c..e126fa37c16151414af19267ae18055a990d4ed9 100644 (file)
@@ -3406,12 +3406,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor,
 static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor,
                                    struct spi_nor_flash_parameter *params)
 {
-       /* READ_1_1_2 is not supported */
-       params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
-       /* READ_1_1_4 is not supported */
-       params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
-       /* PP_1_1_4 is not supported */
-       params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+       /*
+        * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for
+        * read ops in SFDP are wrong. The other density parts do not support
+        * 1-1-2 and 1-1-4 commands.
+        */
+       if (params->size == SZ_8M) {
+               spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_2],
+                                         0, 8, SPINOR_OP_READ_1_1_2,
+                                         SNOR_PROTO_1_1_2);
+               spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_1_4],
+                                         0, 8, SPINOR_OP_READ_1_1_4,
+                                         SNOR_PROTO_1_1_4);
+       } else {
+               params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2;
+               params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4;
+               params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4;
+       }
+
        /* Use volatile register to enable quad */
        params->quad_enable = s25fs_s_quad_enable;
 }
index 17e0f84e9eeb922ca965cdccfd5de7608f0b266e..9693c179b7edfbcc41ae2bd2e92bc6330de2d877 100644 (file)
@@ -342,6 +342,9 @@ const struct flash_info spi_nor_ids[] = {
        { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
        { INFO6("s25fl256s1", 0x010219, 0x4d0180,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
        { INFO6("s25fl512s",  0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+       { INFO6("s25fs064s",  0x010217, 0x4d0181,  64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+       { INFO6("s25fs128s",  0x012018, 0x4d0181,  64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+       { INFO6("s25fs256s",  0x010219, 0x4d0181,  64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
        { INFO6("s25fs512s",  0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
        { INFO("s25fl512s_256k",  0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
        { INFO("s25fl512s_64k",  0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },