microblaze: start.S: add support for configurable vector base address

Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze, so update the
__setup_exceptions routine to work with any vector base address.

The r4 register is reserved for the vector base address inside
__setup_exceptions and the function prologe/epilogue are also updated to
save and restore r4.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 68f97f426cbdc97e3a3aed67a9fc5940057cbcb2..645f7cb0389d768a0a29e9968310ba096b245485 100644 (file)
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -105,15 +105,17 @@ clear_bss:
  * r10: Stores little/big endian offset for vectors
  * r2: Stores imm opcode
  * r3: Stores brai opcode
+ * r4: Stores the vector base address
  */
 __setup_exceptions:
-       addik   r1, r1, -28
+       addik   r1, r1, -32
        swi     r2, r1, 4
        swi     r3, r1, 8
-       swi     r6, r1, 12
-       swi     r7, r1, 16
-       swi     r8, r1, 20
-       swi     r10, r1, 24
+       swi     r4, r1, 12
+       swi     r6, r1, 16
+       swi     r7, r1, 20
+       swi     r8, r1, 24
+       swi     r10, r1, 28
 
        /* Find-out if u-boot is running on BIG/LITTLE endian platform
         * There are some steps which is necessary to keep in mind:
@@ -132,22 +134,25 @@ __setup_exceptions:
        addi    r2, r0, 0xb0000000      /* hex b000 opcode imm */
        addi    r3, r0, 0xb8080000      /* hew b808 opcode brai */
 
+       /* Store the vector base address in r4 */
+       addi    r4, r0, CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
+
        /* reset address */
-       swi     r2, r0, 0x0     /* reset address - imm opcode */
-       swi     r3, r0, 0x4     /* reset address - brai opcode */
+       swi     r2, r4, 0x0     /* reset address - imm opcode */
+       swi     r3, r4, 0x4     /* reset address - brai opcode */
 
        addik   r6, r0, CONFIG_SYS_TEXT_BASE
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x2
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x6
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 
 #if CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USR_EXCEP)
        /* user_vector_exception */
-       swi     r2, r0, 0x8     /* user vector exception - imm opcode */
-       swi     r3, r0, 0xC     /* user vector exception - brai opcode */
+       swi     r2, r4, 0x8     /* user vector exception - imm opcode */
+       swi     r3, r4, 0xC     /* user vector exception - brai opcode */
 
        addik   r6, r5, _exception_handler
        sw      r6, r1, r0
@@ -173,42 +178,43 @@ __setup_exceptions:
         */
        lhu     r7, r1, r10
        rsubi   r8, r10, 0xa
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0xe
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 #endif
 
        /* interrupt_handler */
-       swi     r2, r0, 0x10    /* interrupt - imm opcode */
-       swi     r3, r0, 0x14    /* interrupt - brai opcode */
+       swi     r2, r4, 0x10    /* interrupt - imm opcode */
+       swi     r3, r4, 0x14    /* interrupt - brai opcode */
 
        addik   r6, r5, _interrupt_handler
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x12
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x16
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 
        /* hardware exception */
-       swi     r2, r0, 0x20    /* hardware exception - imm opcode */
-       swi     r3, r0, 0x24    /* hardware exception - brai opcode */
+       swi     r2, r4, 0x20    /* hardware exception - imm opcode */
+       swi     r3, r4, 0x24    /* hardware exception - brai opcode */
 
        addik   r6, r5, _hw_exception_handler
        sw      r6, r1, r0
        lhu     r7, r1, r10
        rsubi   r8, r10, 0x22
-       sh      r7, r0, r8
+       sh      r7, r4, r8
        rsubi   r8, r10, 0x26
-       sh      r6, r0, r8
+       sh      r6, r4, r8
 
-       lwi     r10, r1, 24
-       lwi     r8, r1, 20
-       lwi     r7, r1, 16
-       lwi     r6, r1, 12
+       lwi     r10, r1, 28
+       lwi     r8, r1, 24
+       lwi     r7, r1, 20
+       lwi     r6, r1, 16
+       lwi     r4, r1, 12
        lwi     r3, r1, 8
        lwi     r2, r1, 4
-       addik   r1, r1, 28
+       addik   r1, r1, 32
 
        rtsd    r15, 8
        or      r0, r0, r0