arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi

The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.

Fixes: 24a7a3c1c042 ("imx8mm: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>

diff --git a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
index 11c773bb70d6779a0271d5d1ee1ce58f20001e89..dc99e7b9ac6cbf2bc2d904b40a146c336ffd7d64 100644 (file)
--- a/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
@@ -129,6 +129,57 @@
        phy-reset-post-delay = <1>;
 };
 
+&switch {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               lan1: port@0 {
+                       phy-handle = <&sw_phy0>;
+               };
+
+               lan2: port@1 {
+                       phy-handle = <&sw_phy1>;
+               };
+
+               lan3: port@2 {
+                       phy-handle = <&sw_phy2>;
+               };
+
+               lan4: port@3 {
+                       phy-handle = <&sw_phy3>;
+               };
+       };
+
+       mdios {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               mdio@0 {
+                       reg = <0>;
+                       compatible = "microchip,ksz-mdio";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       sw_phy0: ethernet-phy@0 {
+                               reg = <0x0>;
+                       };
+
+                       sw_phy1: ethernet-phy@1 {
+                               reg = <0x1>;
+                       };
+
+                       sw_phy2: ethernet-phy@2 {
+                               reg = <0x2>;
+                       };
+
+                       sw_phy3: ethernet-phy@3 {
+                               reg = <0x3>;
+                       };
+               };
+       };
+};
+
 &pinctrl_fec1 {
        u-boot,dm-spl;
 };