arm64: dts: rockchip: enable sata1+2 on Qnap-TS433

The TS433 has 4 bays. The last two are accessed via a pci-connected
sata controller, while the first two are accessed via the rk3568's
sata controllers. Enable these two now.

Tested-by: Uwe Kleine-König <ukleinek@debian.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240723195538.1133436-7-heiko@sntech.de
[ upstream commit: 673c1353b3d476b9c5df6b84a777ed171e5594f5 ]

(cherry picked from commit dfa45bbda057851d0c2167b4c311c0301637cc19)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
index be1c2286c2d3fbb7ff5d9535aa02d760126888bf..40af4dd0e41587d310604b88e71890572018d352 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3568-qnap-ts433.dts
@@ -80,6 +80,16 @@
        status = "okay";
 };
 
+/* connected to sata1 */
+&combphy1 {
+       status = "okay";
+};
+
+/* connected to sata2 */
+&combphy2 {
+       status = "okay";
+};
+
 &gmac0 {
        assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
        assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
@@ -156,6 +166,14 @@
        };
 };
 
+&sata1 {
+       status = "okay";
+};
+
+&sata2 {
+       status = "okay";
+};
+
 &sdhci {
        bus-width = <8>;
        max-frequency = <200000000>;