]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
omap3: remove remnant macros GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT
authorpekon gupta <pekon@ti.com>
Mon, 5 May 2014 19:16:20 +0000 (00:46 +0530)
committerTom Rini <trini@ti.com>
Fri, 6 Jun 2014 21:46:07 +0000 (17:46 -0400)
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.

Signed-off-by: Pekon Gupta <pekon@ti.com>
arch/arm/cpu/armv7/omap3/mem.c
arch/arm/include/asm/arch-omap3/mem.h
board/compulab/cm_t35/cm_t35.c
include/configs/cm_t335.h
include/configs/cm_t35.h
include/configs/pengwyn.h
include/configs/tao3530.h
include/configs/tseries.h

index e64940965447d10d110ba445b844fe3d4085456a..1832affa5bbb2959a64f794d22bf6468b0ecbcf6 100644 (file)
 struct gpmc *gpmc_cfg;
 
 #if defined(CONFIG_CMD_NAND)
-#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
-static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
-       0,
-};
-#else
 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG1,
        M_NAND_GPMC_CONFIG2,
@@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
        M_NAND_GPMC_CONFIG5,
        M_NAND_GPMC_CONFIG6, 0
 };
-#endif
 #endif /* CONFIG_CMD_NAND */
 
 #if defined(CONFIG_CMD_ONENAND)
index bdb1435291a1b9ea85211d108f2304a28128bb77..d2dfb1e19aaf335cdb2984bc6b4182e12a5d53e9 100644 (file)
@@ -354,14 +354,6 @@ enum {
 
 #define GPMC_CS_ENABLE         0x1
 
-#define SMNAND_GPMC_CONFIG1    0x00000800
-#define SMNAND_GPMC_CONFIG2    0x00141400
-#define SMNAND_GPMC_CONFIG3    0x00141400
-#define SMNAND_GPMC_CONFIG4    0x0F010F01
-#define SMNAND_GPMC_CONFIG5    0x010C1414
-#define SMNAND_GPMC_CONFIG6    0x1F0F0A80
-#define SMNAND_GPMC_CONFIG7    0x00000C44
-
 #define M_NAND_GPMC_CONFIG1    0x00001800
 #define M_NAND_GPMC_CONFIG2    0x00141400
 #define M_NAND_GPMC_CONFIG3    0x00141400
index 00bcf41bb3b84d44b9abe9488914658460307767..0944903ec8882005b096d8ca7c8750dd1d8a53d8 100644 (file)
@@ -54,12 +54,12 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
 };
 
 static u32 gpmc_nand_config[GPMC_MAX_REG] = {
-       SMNAND_GPMC_CONFIG1,
-       SMNAND_GPMC_CONFIG2,
-       SMNAND_GPMC_CONFIG3,
-       SMNAND_GPMC_CONFIG4,
-       SMNAND_GPMC_CONFIG5,
-       SMNAND_GPMC_CONFIG6,
+       M_NAND_GPMC_CONFIG1,
+       M_NAND_GPMC_CONFIG2,
+       M_NAND_GPMC_CONFIG3,
+       M_NAND_GPMC_CONFIG4,
+       M_NAND_GPMC_CONFIG5,
+       M_NAND_GPMC_CONFIG6,
        0,
 };
 
index 26b615b8c507428e54bdc10da70d376e29e5ed57..4d1dd28a9150105da2b4825be5e374d01b71ded6 100644 (file)
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x200000
 
 #define CONFIG_CMD_NAND
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
 #define MTDIDS_DEFAULT                 "nand0=nand"
 #define MTDPARTS_DEFAULT               "mtdparts=nand:2m(spl)," \
                                        "1m(u-boot),1m(u-boot-env)," \
index aae05e0333039c2647fc1571ed04d38f80d61888..8c60e22c1dd053e5e98c1deff068b470c6066469 100644 (file)
                                                        /* CS0 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
-#define GPMC_NAND_ECC_LP_x8_LAYOUT
 
 /* Environment information */
 #define CONFIG_BOOTDELAY               3
index fc25966e0f214c57e24d44b4dcaef5872e78bb3e..85104057a96465bc38befb75e03763f5aa5e61ae 100644 (file)
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 
-#define GPMC_NAND_ECC_LP_x8_LAYOUT     1
 #define MTDIDS_DEFAULT                 "nand0=omap2-nand.0"
 #define MTDPARTS_DEFAULT               "mtdparts=omap2-nand.0:128k(SPL)," \
                                        "128k(SPL.backup1)," \
index 4471935287882605cb21b1af9028039b4c74d151..1b0fee9a8085f8bbd0d276fcc4f6ccad2a347e3d 100644 (file)
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access nand at */
                                                        /* CS0 */
-#define GPMC_NAND_ECC_LP_x16_LAYOUT
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
index e550afad4fa13b680500c75d2921bd319d4432a8..1fd6e32bafc96c52f7dce86958196b072c461378 100644 (file)
 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
 #define CONFIG_NAND_OMAP_ELM
 #define CONFIG_NAND_OMAP_ECCSCHEME     OMAP_ECC_BCH8_CODE_HW
-#define GPMC_NAND_ECC_LP_x16_LAYOUT    1
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128*1024)
 #define CONFIG_SYS_NAND_PAGE_SIZE      2048