arm64: dts: ti: iot2050: Add overlays for M.2 used by firmware

To allow firmware to pick up all DTs from here, move the overlays that
are normally applied during DT fixup to the kernel source as well. Hook
then into the build nevertheless to ensure that regular checks are
performed.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/91f8b825467651ebd51a4051f153ab136eeb1849.1724830741.git.jan.kiszka@siemens.com
Signed-off-by: Nishanth Menon <nm@ti.com>
[ upstream commit: dba27d026fc841d28a0ed373f617cc84ec0e4504 ]

(cherry picked from commit 741915246a92fc4c21537f9623a69612f7cef03a)

diff --git a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
new file mode 100644 (file)
index 0000000..666237f
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtso
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IOT2050 M.2 variant, overlay for B-key PCIE0_LANE0 + E-key PCIE1_LANE0
+ * Copyright (c) Siemens AG, 2022-2024
+ *
+ * Authors:
+ *   Chao Zeng <chao.zeng@siemens.com>
+ *   Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&pcie0_rc {
+       num-lanes = <1>;
+       phys = <&serdes0 PHY_TYPE_PCIE 1>;
+       phy-names = "pcie-phy0";
+       reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&pcie1_rc {
+       status = "okay";
+};

diff --git a/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
new file mode 100644 (file)
index 0000000..0f86235
--- /dev/null
+++ b/dts/upstream/src/arm64/ti/k3-am6548-iot2050-advanced-m2-bkey-usb3.dtso
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * IOT2050 M.2 variant, overlay for B-key USB3.0 + E-key PCIE1_LANE0
+ * Copyright (c) Siemens AG, 2022-2024
+ *
+ * Authors:
+ *   Chao Zeng <chao.zeng@siemens.com>
+ *   Jan Kiszka <jan.kiszka@siemens.com>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&serdes0 {
+       assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
+};
+
+&pcie0_rc {
+       status = "disabled";
+};
+
+&pcie1_rc {
+       pinctrl-names = "default";
+       pinctrl-0 = <&minipcie_pins_default>;
+
+       num-lanes = <1>;
+       phys = <&serdes1 PHY_TYPE_PCIE 0>;
+       phy-names = "pcie-phy0";
+       reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
+&dwc3_0 {
+       assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
+                                <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
+       phys = <&serdes0 PHY_TYPE_USB3 0>;
+       phy-names = "usb3-phy";
+};
+
+&usb0 {
+       maximum-speed = "super-speed";
+       snps,dis-u1-entry-quirk;
+       snps,dis-u2-entry-quirk;
+};