zynqmp: gpio: Add support for zynqmp gpio modepin driver

ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com

diff --git a/MAINTAINERS b/MAINTAINERS
index e718ad21355363c2210c1703df861f28a61a1e31..b3b5c1c17004d5e20dcd143c0d519adb59332c89 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -602,6 +602,7 @@ F:  drivers/clk/clk_zynqmp.c
 F:     driver/firmware/firmware-zynqmp.c
 F:     drivers/fpga/zynqpl.c
 F:     drivers/gpio/zynq_gpio.c
+F:     drivers/gpio/zynqmp_gpio_modepin.c
 F:     drivers/i2c/i2c-cdns.c
 F:     drivers/i2c/muxes/pca954x.c
 F:     drivers/i2c/zynq_i2c.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837feb4800c1caa568b0ba445ae81e1e413..23d57ca10c5171eb26636de4368cafa62c8ef844 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1214,6 +1214,7 @@ config ARCH_ZYNQMP
        imply FAT_WRITE
        imply MP
        imply DM_USB_GADGET
+       imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
 
 config ARCH_TEGRA
        bool "NVIDIA Tegra"

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 40abc33772eb0a174d652ee806119a23bed37e17..8192ce5f676f8bafb040289cb76bf2a5417e7645 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -523,4 +523,13 @@ config NOMADIK_GPIO
          into a number of banks each with 32 GPIOs. The GPIOs for a device are
          defined in the device tree with one node for each bank.
 
+config ZYNQMP_GPIO_MODEPIN
+       bool "ZynqMP gpio modepin"
+       depends on DM_GPIO
+       help
+         This config enables the ZynqMP gpio modepin driver. ZynqMP modepin
+         driver will set and get the status of PS_MODE pins. These modepins
+         are accessed using xilinx firmware. In modepin register, [3:0] bits
+         set direction, [7:4] bits read IO, [11:8] bits set/clear IO.
+
 endif

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3c851b38c7ccc10ef70967f4d8f5865c703674d0..3eb77f58c11de0b5a47a9cdd202e1ab97f620448 100644 (file)
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_NX_GPIO)         += nx_gpio.o
 obj-$(CONFIG_SIFIVE_GPIO)      += sifive-gpio.o
 obj-$(CONFIG_NOMADIK_GPIO)     += nmk_gpio.o
 obj-$(CONFIG_MAX7320_GPIO)     += max7320_gpio.o
+obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN)      += zynqmp_gpio_modepin.o

diff --git a/drivers/gpio/zynqmp_gpio_modepin.c b/drivers/gpio/zynqmp_gpio_modepin.c
new file mode 100644 (file)
index 0000000..078fd83
--- /dev/null
+++ b/drivers/gpio/zynqmp_gpio_modepin.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ZynqMP GPIO modepin driver
+ *
+ * Copyright (C) 2021 Xilinx, Inc.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <dm.h>
+#include <asm/arch/hardware.h>
+#include <zynqmp_firmware.h>
+
+#define OUTEN(pin)             (BIT(0) << (pin))
+#define INVAL(pin)             (BIT(4) << (pin))
+#define OUTVAL(pin)            (BIT(8) << (pin))
+
+#define ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK       0xF0F
+#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL           (ZYNQMP_CRL_APB_BASEADDR + \
+                                               (0x250U))
+
+static int get_gpio_modepin(u32 *ret_payload)
+{
+       return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
+                                0, 0, 0, ret_payload);
+}
+
+static int set_gpio_modepin(int val)
+{
+       return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
+                                ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
+                                val, 0, NULL);
+}
+
+static int modepin_gpio_direction_input(struct udevice *dev,
+                                       unsigned int offset)
+{
+       return 0;
+}
+
+static int modepin_gpio_set_value(struct udevice *dev, unsigned int offset,
+                                 int value)
+{
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       u32 out_val = 0;
+       int ret;
+
+       ret = get_gpio_modepin(ret_payload);
+       if (value)
+               out_val = OUTVAL(offset) | ret_payload[1];
+       else
+               out_val = ~OUTVAL(offset) & ret_payload[1];
+
+       return set_gpio_modepin(out_val);
+}
+
+static int modepin_gpio_direction_output(struct udevice *dev,
+                                        unsigned int offset, int value)
+{
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       u32 out_en = 0;
+       int ret;
+
+       ret = get_gpio_modepin(ret_payload);
+       if (ret)
+               return ret;
+
+       if (value)
+               out_en = OUTEN(offset) | ret_payload[1];
+       else
+               out_en = ~OUTEN(offset) & ret_payload[1];
+
+       ret = set_gpio_modepin(out_en);
+       if (ret)
+               return ret;
+
+       return modepin_gpio_set_value(dev, offset, value);
+}
+
+static int modepin_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+                             struct ofnode_phandle_args *args)
+{
+       desc->offset = args->args[0];
+
+       return 0;
+}
+
+static int modepin_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       int ret;
+
+       ret = get_gpio_modepin(ret_payload);
+       if (ret)
+               return ret;
+
+       return (INVAL(offset) & ret_payload[1]) ? 1 : 0;
+}
+
+static int modepin_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+       u32 ret_payload[PAYLOAD_ARG_CNT];
+       int ret;
+
+       ret = get_gpio_modepin(ret_payload);
+       if (ret)
+               return ret;
+
+       return (OUTEN(offset) & ret_payload[1]) ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static const struct dm_gpio_ops modepin_gpio_ops = {
+       .direction_input = modepin_gpio_direction_input,
+       .direction_output = modepin_gpio_direction_output,
+       .get_value = modepin_gpio_get_value,
+       .set_value = modepin_gpio_set_value,
+       .get_function = modepin_gpio_get_function,
+       .xlate = modepin_gpio_xlate,
+};
+
+static int modepin_gpio_probe(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       const void *label_ptr;
+
+       label_ptr = dev_read_prop(dev, "label", NULL);
+       if (label_ptr) {
+               uc_priv->bank_name = strdup(label_ptr);
+               if (!uc_priv->bank_name)
+                       return -ENOMEM;
+       } else {
+               uc_priv->bank_name = dev->name;
+       }
+
+       uc_priv->gpio_count = 4;
+
+       return 0;
+}
+
+static const struct udevice_id modepin_gpio_ids[] = {
+       { .compatible = "xlnx,zynqmp-gpio-modepin",},
+       { }
+};
+
+U_BOOT_DRIVER(modepin_gpio) = {
+       .name = "modepin_gpio",
+       .id = UCLASS_GPIO,
+       .ops = &modepin_gpio_ops,
+       .of_match = modepin_gpio_ids,
+       .probe = modepin_gpio_probe,
+};