ifndef CONFIG_TPL_BUILD
ifndef CONFIG_VPL_BUILD
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_CPU) += cpu/
obj-$(CONFIG_SPL_CRYPTO) += crypto/
endif
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += ata/
obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_SPL_LEGACY_BLOCK) += blk_legacy.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_IDE) += ide.o
obj-$(CONFIG_RKMTD) += rkmtd.o
endif
# Makefile for the bus drivers.
#
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_TI_PWMSS) += ti-pwmss.o
obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
endif
if (!cfg)
return;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
} else {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
if (!cfg)
return;
-#if IS_ENABLED(CONFIG_SPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD)
/* Always force clock manager into boot mode before any configuration */
clk_write_ctrl(plat,
CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
* However, still set them for SPL. And still set them if explicitly
* asked.
*/
- if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
+ if (!(IS_ENABLED(CONFIG_XPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
if (stage != CLK_DEFAULTS_POST_FORCE)
return 0;
return data;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)
{
int err;
static struct clk_ops vexpress_osc_clk_ops = {
.get_rate = vexpress_osc_clk_get_rate,
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
.set_rate = vexpress_osc_clk_set_rate,
#endif
};
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
enum zynq_clk_rclk {mio_clk, emio_clk};
#endif
struct zynq_clk_priv {
ulong ps_clk_freq;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
struct clk gem_emio_clk[2];
#endif
};
return &slcr_base->uart_clk_ctrl;
case spi0_clk ... spi1_clk:
return &slcr_base->spi_clk_ctrl;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case dci_clk:
return &slcr_base->dci_clk_ctrl;
case gem0_clk:
return priv->ps_clk_freq * mul;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id)
{
u32 clk_ctrl, srcsel;
return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv)
{
u32 clk_ctrl, div;
return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv)
{
u32 clk_ctrl, div0, div1;
if (!div0)
div0 = 1;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (two_divs) {
div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
if (!div1)
div1);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
{
struct clk *parent;
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong zynq_clk_get_rate(struct clk *clk)
{
struct zynq_clk_priv *priv = dev_get_priv(clk->dev);
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
.enable = dummy_enable,
static int zynq_clk_probe(struct udevice *dev)
{
struct zynq_clk_priv *priv = dev_get_priv(dev);
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
unsigned int i;
char name[16];
int ret;
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
"audio_pll1_out", "video_pll1_out", };
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static const char * const imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m",
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll1_out", "sys_pll3_out", };
"sys_pll1_160m", "sys_pll1_200m", };
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static const char * const imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll1_out", };
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MM_CLK_ENET_AXI,
imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
base + 0x8880));
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
"video_pll_out", "sys_pll3_out", };
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static const char * const imx8mn_enet_ref_sels[] = {"clock-osc-24m", "sys_pll2_125m", "sys_pll2_50m",
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
"video_pll_out", "clk_ext4", };
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
"audio_pll2_out", "sys_pll1_133m", };
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static const char * const imx8mn_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m",
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
"sys_pll1_80m", "video_pll_out", };
imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
/* clks not needed in SPL stage */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
clk_dm(IMX8MN_CLK_ENET_REF,
imx8m_clk_composite("enet_ref", imx8mn_enet_ref_sels,
base + 0xa980));
clk_dm(IMXRT1020_CLK_SEMC,
imx_clk_gate2("semc", "semc_podf", base + 0x74, 4));
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct clk *clk, *clk1;
clk_get_by_id(IMXRT1020_CLK_SEMC_SEL, &clk1);
struct clk *clk, *clk1;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* bypass pll1 before setting its rate */
clk_get_by_id(IMXRT1050_CLK_PLL1_REF_SEL, &clk);
clk_get_by_id(IMXRT1050_CLK_PLL1_BYPASS, &clk1);
return px30_peri_get_clk(priv, clk_id);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong px30_crypto_get_clk(struct px30_clk_priv *priv, ulong clk_id)
{
struct px30_cru *cru = priv->cru;
case HCLK_PERI_PRE:
rate = px30_peri_get_clk(priv, clk->id);
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case SCLK_CRYPTO:
case SCLK_CRYPTO_APK:
rate = px30_crypto_get_clk(priv, clk->id);
case HCLK_PERI_PRE:
ret = px30_peri_set_clk(priv, clk->id, rate);
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case SCLK_CRYPTO:
case SCLK_CRYPTO_APK:
ret = px30_crypto_set_clk(priv, clk->id, rate);
"divisors on line " __stringify(__LINE__));
/* Keep divisors as low as possible to reduce jitter and power usage */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
#endif
return rockchip_spi_get_clk(cru, gclk_rate, periph);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf,
bool has_bwadj)
{
return PTR_ERR(priv->grf);
priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_plat *plat = dev_get_plat(dev);
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#define VCO_MAX_KHZ 2200000
#define VCO_MIN_KHZ 440000
#define FREF_MAX_KHZ 2200000
return rockchip_i2s_get_clk(cru, gclk_rate);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
{
case SCLK_SPI2:
new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case SCLK_I2S0:
new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
break;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (IS_ERR(priv->grf))
return PTR_ERR(priv->grf);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_plat *plat = dev_get_plat(dev);
return rk3328_spi_get_clk(cru);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id)
{
struct rk3328_cru *cru = priv->cru;
case SCLK_SPI:
ret = rk3328_spi_set_clk(priv->cru, rate);
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case DCLK_LCDC:
case ACLK_VOP_PRE:
case ACLK_VIO_PRE:
(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
"divisors on line " __stringify(__LINE__));
-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
#if !defined(CONFIG_TPL_BUILD)
}
}
-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
const struct pll_div *div)
{
}
#endif
-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
static void rkclk_init(struct rk3368_cru *cru)
{
u32 apllb, aplll, dpll, cpll, gpll;
}
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
u32 div, con, con_id, rate;
case SCLK_SPI0 ... SCLK_SPI2:
rate = rk3368_spi_get_clk(priv->cru, clk->id);
break;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
rate = rk3368_mmc_get_clk(priv->cru, clk->id);
ret = rk3368_ddr_set_clk(priv->cru, rate);
break;
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(MMC)
case HCLK_SDMMC:
case HCLK_EMMC:
ret = rk3368_mmc_set_clk(clk, rate);
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
-#if IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
+#if IS_ENABLED(CONFIG_XPL_BUILD) || IS_ENABLED(CONFIG_TPL_BUILD)
rkclk_init(priv->cru);
#endif
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
#endif
priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
init_clocks = true;
#elif CONFIG_IS_ENABLED(HANDOFF)
if (!(gd->flags & GD_FLG_RELOC)) {
.set_rate = rk3399_pmuclk_set_rate,
};
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static void pmuclk_init(struct rk3399_pmucru *pmucru)
{
u32 pclk_div;
static int rk3399_pmuclk_probe(struct udevice *dev)
{
-#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_XPL_BUILD)
struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
#endif
priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
pmuclk_init(priv->pmucru);
#endif
return 0;
RK3568_PMU_MODE, 2, 10, 0, rk3568_pll_rates),
};
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong
rk3568_pmu_pll_set_rate(struct rk3568_clk_priv *priv,
ulong pll_id, ulong rate)
return rk3568_emmc_get_bclk(priv);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong rk3568_aclk_vop_get_clk(struct rk3568_clk_priv *priv)
{
struct rk3568_cru *cru = priv->cru;
case TCLK_EMMC:
rate = OSC_HZ;
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case ACLK_VOP:
rate = rk3568_aclk_vop_get_clk(priv);
break;
case TCLK_EMMC:
ret = OSC_HZ;
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case ACLK_VOP:
ret = rk3568_aclk_vop_set_clk(priv, rate);
break;
priv->gpll_hz = GPLL_HZ;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
ret = rk3568_bus_set_clk(priv, ACLK_BUS, 150000000);
if (ret < 0)
printf("Fail to set the ACLK_BUS clock.\n");
RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
[PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),
RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* The SPLL is part of the SBUSCRU, not the main CRU and as
* such only directly accessible during the SPL stage.
};
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
*
* rational_best_approximation(31415, 10000,
return rk3588_mmc_get_clk(priv, clk_id);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id)
{
struct rk3588_cru *cru = priv->cru;
case CLK_GPU:
rate = 200000000;
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
rate = rk3588_aux16m_get_clk(priv, clk->id);
case CLK_150M_SRC:
ret = 0;
break;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
case CLK_AUX16M_0:
case CLK_AUX16M_1:
ret = rk3588_aux16m_set_clk(priv, clk->id, rate);
priv->sync_kernel = false;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru,
B0PLL, LPLL_HZ);
rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru,
.probe = rk3588_clk_probe,
};
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define SCRU_BASE 0xfd7d0000
#define SBUSCRU_BASE 0xfd7d8000
__prci_wrpll_read_cfg0(pd, pc->pwd);
}
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
if (device_is_compatible(dev, "sifive,fu740-c000-prci")) {
u32 prci_pll_reg;
unsigned long parent_rate;
return ERR_PTR(ret);
}
- if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL0)
+ if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL0)
jh7110_pllx_set_rate(clk, 1000000000);
- if (IS_ENABLED(CONFIG_SPL_BUILD) && pll->type == PLL2)
+ if (IS_ENABLED(CONFIG_XPL_BUILD) && pll->type == PLL2)
jh7110_pllx_set_rate(clk, 1188000000);
return clk;
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT
#endif
dev_err(dev, "clock tree initialization failed (%d)\n", result);
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#if defined(VERBOSE_DEBUG)
/* display debug information for probe after relocation */
if (gd->flags & GD_FLG_RELOC)
.disable = stm32mp1_clk_disable,
.get_rate = stm32mp1_clk_get_rate,
.set_rate = stm32mp1_clk_set_rate,
-#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_SPL_BUILD)
+#if IS_ENABLED(CONFIG_CMD_CLK) && !IS_ENABLED(CONFIG_XPL_BUILD)
.dump = stm32mp1_clk_dump,
#endif
};
out_values, sz);
/* get the error right, but space is more important in SPL */
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
if (ret == -FDT_ERR_NOTFOUND)
return -EINVAL;
else if (ret == -FDT_ERR_BADLAYOUT)
bool ofnode_pre_reloc(ofnode node)
{
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_TPL_BUILD)
+#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_TPL_BUILD)
/* for SPL and TPL the remaining nodes after the fdtgrep 1st pass
* had property bootph-all or bootph-pre-sram/bootph-pre-ram.
* They are removed in final dtb (fdtgrep 2nd pass)
append_store(desc, dma_addr_out, storelen,
LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr,
uint8_t *plain_txt, uint8_t *enc_blob,
uint32_t in_sz)
ccsr_sec_t *sec = caam->sec;
uint32_t mcr = sec_in32(&sec->mcfgr);
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M)
uint32_t jrdid_ms = 0;
#endif
#ifdef CONFIG_FSL_CORENET
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX8M)
jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID;
sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms);
#endif
jr_reset();
#ifdef CONFIG_FSL_CORENET
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* For SPL Build, Set the Liodns in SEC JR0 for
* creating PAMU entries corresponding to these.
#include "sequencer.h"
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct altera_gen5_sdram_priv {
struct ram_info info;
.priv_auto = sizeof(struct altera_gen5_sdram_priv),
};
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
if (dimm_params[i].n_ranks) {
if (dimm_params[i].registered_dimm) {
temp1 = 1;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("Detected RDIMM %s\n",
dimm_params[i].mpart);
#endif
} else {
temp2 = 1;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("Detected UDIMM %s\n",
dimm_params[i].mpart);
#endif
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
puts(" ");
#endif
}
if ((first_ctrl == 0) && (total_memory - 1 > (phys_size_t)~0ULL)) {
puts("Detected ");
print_size(total_memory, " of memory\n");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
puts("This U-Boot only supports <= ");
print_size((unsigned long long)((phys_size_t)~0ULL)+1, " of DDR\n");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
puts("You could rebuild it with CONFIG_PHYS_64BIT\n");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
puts(" "); /* re-align to match init_dram print */
#endif
}
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX8M_DRAM) += ddr_init.o
obj-y += ../phy/
endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX8ULP_DRAM) += ddr_init.o
endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX9_DRAM) += ddr_init.o
obj-y += ../phy/
endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_IMX_SNPS_DDR_PHY) += helper.o ddrphy_utils.o ddrphy_train.o ddrphy_csr.o
endif
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_plat.o
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_sys_env_lib.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_build_message.o
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_common.o
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_spd.o
-obj-$(CONFIG_SPL_BUILD) += mv_ddr_topology.o
-obj-$(CONFIG_SPL_BUILD) += xor.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_plat.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_sys_env_lib.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_build_message.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_common.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_spd.o
+obj-$(CONFIG_XPL_BUILD) += mv_ddr_topology.o
+obj-$(CONFIG_XPL_BUILD) += xor.o
obj-$(CONFIG_ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING) += old/
ifdef CONFIG_DDR4
- obj-$(CONFIG_SPL_BUILD) += mv_ddr4_mpr_pda_if.o
- obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training.o
- obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_calibration.o
- obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_db.o
- obj-$(CONFIG_SPL_BUILD) += mv_ddr4_training_leveling.o
+ obj-$(CONFIG_XPL_BUILD) += mv_ddr4_mpr_pda_if.o
+ obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training.o
+ obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_calibration.o
+ obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_db.o
+ obj-$(CONFIG_XPL_BUILD) += mv_ddr4_training_leveling.o
endif
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SPL_BUILD) += ddr3_a38x.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_a38x_training.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_debug.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_hws_hw_training.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_bist.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_centralization.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_db.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_hw_algo.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_ip_engine.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_leveling.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_pbs.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_training_static.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_a38x.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_a38x_training.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_debug.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_hws_hw_training.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_bist.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_centralization.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_db.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_hw_algo.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_ip_engine.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_leveling.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_pbs.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_training_static.o
define IncludeSymbolRename
CFLAGS_$(1) = -include $(srctree)/drivers/ddr/marvell/a38x/old/glue_symbol_renames.h
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += ddr3_dfs.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_dqs.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_hw_training.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_init.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_pbs.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_read_leveling.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_sdram.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_spd.o
-obj-$(CONFIG_SPL_BUILD) += ddr3_write_leveling.o
-obj-$(CONFIG_SPL_BUILD) += xor.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_dfs.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_dqs.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_hw_training.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_init.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_pbs.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_read_leveling.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_sdram.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_spd.o
+obj-$(CONFIG_XPL_BUILD) += ddr3_write_leveling.o
+obj-$(CONFIG_XPL_BUILD) += xor.o
int err;
u32 ret_payload[PAYLOAD_ARG_CNT];
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
printf("Loading new PMUFW cfg obj (%ld bytes)\n", size);
flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size));
if (ret_payload[0])
printf("PMUFW returned 0x%08x status!\n", ret_payload[0]);
- if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_SPL_BUILD))
+ if ((err || ret_payload[0]) && IS_ENABLED(CONFIG_XPL_BUILD))
panic("PMUFW config object loading failed in EL3\n");
return 0;
debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
__func__, current_el(), api_id, arg0, arg1, arg2, arg3);
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
#if defined(CONFIG_ZYNQMP_IPI)
/*
* Use fixed payload and arg size as the EL2 call. The firmware
int ret;
struct udevice *child;
- if ((IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if ((IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||
- (!IS_ENABLED(CONFIG_SPL_BUILD) &&
+ (!IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) {
ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
"zynqmp_power_domain",
#define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
#define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
#define BITSTREAM_CHUNK_SIZE 0xFFFF0
#define RECONFIG_STATUS_POLL_RETRY_MAX 100
if (bstype != BIT_PARTIAL)
zynq_slcr_devcfg_enable();
- if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
puts("INFO:post config was not run, please run manually if needed\n");
return FPGA_SUCCESS;
}
-#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
fpga_fs_info *fsinfo)
{
struct xilinx_fpga_op zynq_op = {
.load = zynq_load,
-#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_XPL_BUILD)
.loadfs = zynq_loadfs,
#endif
};
# Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
obj-$(CONFIG_DM_74X164) += 74x164_gpio.o
static int dm_gpio_requestf(struct gpio_desc *desc, const char *fmt, ...)
{
-#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
+#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
va_list args;
char buf[40];
*/
int gpio_requestf(unsigned gpio, const char *fmt, ...)
{
-#if !defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
+#if !defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(USE_TINY_PRINTF)
va_list args;
char buf[40];
return (int)val;
}
-#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_PCA953X) && !defined(CONFIG_XPL_BUILD)
/*
* Display pca953x information
*/
}
/* Simple SPL interface to GPIOs */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
enum {
PULL_NONE_1V8 = 0,
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
static int rockchip_gpio_probe(struct udevice *dev)
{
writel(value, &bank->dat);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Common GPIO API - SPL does not support driver model yet */
int gpio_set_value(unsigned gpio, int value)
{
value = readl(&bank->dat);
return !!(value & DAT_MASK(gpio));
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
{
}
/* Driver model interface */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* set GPIO pin 'gpio' as an input */
static int exynos_gpio_direction_input(struct udevice *dev, unsigned offset)
{
return 0;
}
-#endif /* nCONFIG_SPL_BUILD */
+#endif /* nCONFIG_XPL_BUILD */
/*
* There is no common GPIO API for pull, drv, pin, rate (yet). These
s5p_gpio_get_pin(gpio), mode);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int exynos_gpio_get_function(struct udevice *dev, unsigned offset)
{
struct exynos_bank_info *state = dev_get_priv(dev);
{
unsigned int gpio;
int ret;
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO
+#if !defined CONFIG_XPL_BUILD && defined CONFIG_AXP_GPIO
char lookup[8];
if (strcasecmp(name, "AXP0-VBUS-ENABLE") == 0) {
return ret;
}
-#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_CMD_TCA642X) && !defined(CONFIG_XPL_BUILD)
/*
* Display tca642x information
*/
return 0;
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
bank_count = TEGRA_GPIO_BANKS;
#else
obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o
obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_APPLE_SPI_KEYB) += apple_spi_kbd.o
obj-$(CONFIG_I8042_KEYB) += i8042.o
writel(msg->buf[i], &mbx[i]);
/* Use SMC calls for Exception Level less than 3 where TF-A is available */
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_NOTIFY, 0);
debug("%s, send %ld bytes\n", __func__, msg->len);
msg->buf[i] = readl(&mbx[i]);
/* Ack to remote if EL is not 3 */
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && current_el() < 3) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && current_el() < 3) {
ret = zynqmp_ipi_fw_call(zynqmp, SMC_IPI_MAILBOX_ACK,
IPI_SMC_ACK_EIRQ_MASK);
}
node = dev_ofnode(dev);
- if (IS_ENABLED(CONFIG_SPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || of_machine_is_compatible("xlnx,zynqmp"))
zynqmp->el3_supported = true;
ret = dev_read_u32(dev->parent, "xlnx,ipi-id", &zynqmp->local_id);
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_SANDBOX) += cros_ec_sandbox.o
obj-$(CONFIG_$(SPL_TPL_)CROS_EC_LPC) += cros_ec_lpc.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += sandbox_adder.o
obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
endif
ifdef CONFIG_$(SPL_)DM_I2C
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
obj-$(CONFIG_USB_HUB_USB251XB) += usb251xb.o
endif
endif
ifdef CONFIG_SPL_OF_PLATDATA
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
endif
endif
if (priv->rtc)
dev_set_priv(priv->rtc, priv);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
gsc_banner(dev);
#endif
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
plat->base = (struct mu_type *)CONFIG_MU_BASE_SPL;
#else
plat->base = (struct mu_type *)addr;
obj-$(CONFIG_SUPPORT_EMMC_BOOT) += mmc_boot.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
endif
ret = blk_find_device(UCLASS_MMC, dev_num, &dev);
if (ret) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC Device %d not found\n", dev_num);
#endif
return NULL;
}
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
void print_mmc_devices(char separator)
{
struct udevice *dev;
break;
if (status & MMC_STATUS_MASK) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("Status Error: %#08x\n", status);
#endif
return -ECOMM;
}
if (timeout_ms <= 0) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("Timeout waiting card ready\n");
#endif
return -ETIMEDOUT;
if (blkcnt > 1) {
if (mmc_send_stop_transmission(mmc, false)) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("mmc fail to send stop cmd\n");
#endif
return 0;
return 0;
if ((start + blkcnt) > block_dev->lba) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
start + blkcnt, block_dev->lba);
#endif
mmc->capacity_gp[i] <<= 19;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (part_completed) {
mmc->enh_user_size =
(ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
bdesc->blksz = mmc->read_bl_len;
bdesc->log2blksz = LOG2(bdesc->blksz);
bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
-#if !defined(CONFIG_SPL_BUILD) || \
+#if !defined(CONFIG_XPL_BUILD) || \
(defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
!CONFIG_IS_ENABLED(USE_TINY_PRINTF))
sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
bdesc->revision[0] = 0;
#endif
-#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
+#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
part_init(bdesc);
#endif
err = mmc_send_op_cond(mmc);
if (err) {
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
if (!quiet)
log_err("Card did not respond to voltage select! : %d\n",
err);
#endif
if (no_card) {
mmc->has_init = 0;
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
log_err("MMC: no card present\n");
#endif
return -ENOMEDIUM;
if (ret)
return ret;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
print_mmc_devices(',');
#endif
return m;
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
printf("MMC Device %d not found\n", dev_num);
#endif
list_add_tail(&mmc->link, &mmc_devices);
}
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
void print_mmc_devices(char separator)
{
struct mmc *m;
}
#endif
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#ifdef CONFIG_MMC_TRACE
void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd);
DECLARE_GLOBAL_DATA_PTR;
/* simplify defines to OMAP_HSMMC_USE_GPIO */
-#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
+#if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_XPL_BUILD)) || \
+ (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
#define OMAP_HSMMC_USE_GPIO
#else
#undef OMAP_HSMMC_USE_GPIO
return -EINVAL;
priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
if (!priv->fifo_mode)
priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
#endif
* Disable use of DMA and force use of PIO mode in SPL to fix an issue
* where loading part of TF-A into SRAM using DMA silently fails.
*/
- if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
host->flags &= ~USE_DMA;
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
int ret;
ret = socfpga_secure_reg_write32(SOCFPGA_SECURE_REG_SYSMGR_SOC64_SDMMC,
return false;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
if (IS_ENABLED(CONFIG_ARCH_UNIPHIER) && !IS_ENABLED(CONFIG_ARM64)) {
/*
* For UniPhier ARMv7 SoCs, the stack is allocated in locked
{
#if CONFIG_IS_ENABLED(CLK)
return clk_get_rate(&priv->clk);
-#elif CONFIG_SPL_BUILD
+#elif CONFIG_XPL_BUILD
return 100000000;
#else
return 0;
priv->clk_get_rate = uniphier_sd_clk_get_rate;
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int ret;
ret = clk_get_by_index(dev, 0, &priv->clk);
{
int ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0) {
ret = zynqmp_mmio_write(SD_ITAP_DLY, SD0_ITAPCHGWIN,
SD0_ITAPCHGWIN);
static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
return zynqmp_mmio_write(SD_OTAP_DLY,
SD0_OTAPDLYSEL_MASK,
static inline int zynqmp_dll_reset(u32 node_id, u32 type)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
if (node_id == NODE_SD_0)
return zynqmp_mmio_write(SD_DLL_CTRL, SD0_DLL_RST,
type == PM_DLL_RESET_ASSERT ?
mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o
# U-Boot build
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
ifneq ($(mtd-y),)
obj-y += mtd.o
# SPDX-License-Identifier: GPL-2.0+
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
nandcore-objs := core.o bbt.o
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
obj-$(CONFIG_MTD_RAW_NAND) += raw/
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_SPL_NAND_DRIVERS
NORMAL_DRIVERS=y
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* The following code is for SPL */
static struct mtd_info *mtd;
static struct nand_chip nand_chip;
if (atmel_nand_chip_init(i, base_addr[i]))
log_err("atmel_nand: Fail to initialize #%d chip", i);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
&lpc32xx_nand_mlc_registers->time_reg);
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/**
* lpc32xx_cmd_ctrl - write command to either cmd or data register
pr_err("nand_register returned %i", ret);
}
-#else /* defined(CONFIG_SPL_BUILD) */
+#else /* defined(CONFIG_XPL_BUILD) */
void nand_init(void)
{
return BYTES_PER_PAGE;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
}
};
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CFG_SYS_NAND_ECCSIZE)
/*
return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
}
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/*
* Prepares DMA descriptors for NAND RD/WR operations
* If the size is < 256 Bytes then it is assumed to be
*/
int board_nand_init(struct nand_chip *lpc32xx_chip)
{
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
int ret;
/* Acquire a channel for our use */
lpc32xx_chip->read_byte = lpc32xx_read_byte;
lpc32xx_chip->write_byte = lpc32xx_write_byte;
-#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DMA_LPC32XX) && !defined(CONFIG_XPL_BUILD)
/* Hardware ECC calculation is supported when DMA driver is selected */
lpc32xx_chip->ecc.mode = NAND_ECC_HW;
{
struct nand_chip *chip = mtd_to_nand(mtd);
int ret = 0;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int res;
#endif
nand_release_device(mtd);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* Mark block bad in BBT */
if (chip->bbt) {
res = nand_markbad_bbt(mtd, ofs);
if (!chip->bbt)
return 0;
/* Return info from the table */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
return nand_isreserved_bbt(mtd, ofs);
#else
return 0;
return chip->block_bad(mtd, ofs);
/* Return info from the table */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
return nand_isbad_bbt(mtd, ofs, allowbbt);
#else
return 0;
if (!chip->read_buf || chip->read_buf == nand_read_buf)
chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
if (!chip->scan_bbt)
chip->scan_bbt = nand_default_bbt;
#endif
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* omap_nand_switch_ecc - switch the ECC operation between different engines
* (h/w and s/w) and different algorithms (hamming and BCHx)
err = nand_scan_tail(mtd);
return err;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/*
* Board-specific NAND initialization. The following members of the
log_info("Failed to get sandbox NAND: %d\n", err);
}
-#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
+#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_NAND_INIT)
void nand_deselect(void)
{
nand_chip->select_chip(nand_to_mtd(nand_chip), -1);
# Copyright (C) 2005-2007 Samsung Electronics.
# Kyungmin Park <kyungmin.park@samsung.com>
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
obj-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
else
obj-$(CONFIG_$(SPL_TPL_)DM_SPI_FLASH) += sf-uclass.o
spi-nor-y := sf_probe.o spi-nor-ids.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
ifeq ($(CONFIG_$(SPL_TPL_)SPI_FLASH_TINY),y)
spi-nor-y += spi-nor-tiny.o
struct udevice *bus;
char *str;
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
+#if defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(USE_TINY_PRINTF)
str = "spi_flash";
#else
char name[30];
spi_flash->size = nr_pages * pagesize;
spi_flash->erase_size = pagesize;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
print_size(spi_flash->page_size, ", erase size ");
print_size(spi_flash->erase_size, ", total ");
while (len) {
schedule();
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
goto erase_err;
nor->erase_size = mtd->erasesize;
nor->sector_size = mtd->erasesize;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
printf("SF: Detected %s with page size ", nor->name);
print_size(nor->page_size, ", erase size ");
print_size(nor->erase_size, ", total ");
u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
xgmac->syscon_phy_regshift;
- if (!(IS_ENABLED(CONFIG_SPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ if (!(IS_ENABLED(CONFIG_XPL_BUILD)) && IS_ENABLED(CONFIG_SPL_ATF)) {
u32 index = ((u64)xgmac->syscon_phy - socfpga_get_sysmgr_addr() -
SYSMGR_SOC64_EMAC0) >> 2;
struct dwmac_socfpga_plat *pdata = dev_get_plat(dev);
u32 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
u32 index = ((u64)pdata->phy_intf - socfpga_get_sysmgr_addr() -
SYSMGR_SOC64_EMAC0) >> 2;
};
#if CONFIG_IS_ENABLED(DM_GPIO) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
+ (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
static int mtk_gpio_get(struct udevice *dev, unsigned int off)
{
int val, err;
}
#if CONFIG_IS_ENABLED(DM_GPIO) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
+ (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_GPIO))
ret = mtk_gpiochip_register(dev);
#endif
struct list_head list;
};
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static char pin_name[PINNAME_SIZE];
static const char * const pinmux_mode[GPIOF_COUNT] = {
#else /* PINCTRL_FULL */
.set_state_simple = stm32_pinctrl_set_state_simple,
#endif /* PINCTRL_FULL */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
.get_pin_name = stm32_pinctrl_get_pin_name,
.get_pins_count = stm32_pinctrl_get_pins_count,
.get_pin_muxing = stm32_pinctrl_get_pin_muxing,
# SPDX-License-Identifier: GPL-2.0
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ifdef CONFIG_TEGRA20
obj-y += pinctrl-tegra20.o
else
#define __UNIPHIER_PINMUX_FUNCTION(func) #func
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL,
* suppressing "defined but not used" warnings.
obj-y += regulator/
obj-$(CONFIG_AXP221_POWER) += axp221.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
obj-$(CONFIG_AXP305_POWER) += axp_spl.o
if (!children)
debug("%s: %s - no child found\n", __func__, dev->name);
- if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON))
dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
pmic_reg_read(dev, init_data[i].reg));
}
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
printf("PMIC: RK%x ", show_variant);
if (on_source && off_source)
printf("(on=0x%02x, off=0x%02x)",
dev_dbg(dev, "no child found\n");
#endif /* DM_REGULATOR */
- if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD)) {
ret = device_bind_driver(dev, "stpmic1-nvm",
"stpmic1-nvm", NULL);
if (ret)
.ops = &stpmic1_ops,
};
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int stpmic1_nvm_rw(struct udevice *dev, u8 addr, u8 *buf, int buf_len,
enum pmic_nvm_op op)
{
.id = UCLASS_MISC,
.ops = &stpmic1_nvm_ops,
};
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#ifdef CONFIG_SYSRESET
static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type)
return NULL;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int pmic_dump(struct pmic *p)
{
int i, ret;
#include <power/pmic.h>
#include <power/regulator.h>
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#define ENABLE_DRIVER
#endif
#define SY8106A_VOUT1_SEL 1
#define SY8106A_VOUT1_SEL_ENABLE (1 << 7)
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static u8 sy8106a_mvolt_to_cfg(int mvolt, int min, int max, int div)
{
if (mvolt < min)
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
obj-$(CONFIG_RAM_SIFIVE) += sifive/
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive/
endif
struct clk mem_mux;
};
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static int mtk_ddr3_rank_size_detect(struct udevice *dev)
{
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
if (priv->dramc_ao == FDT_ADDR_T_NONE)
return -EINVAL;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int ret;
ret = clk_get_by_index(dev, 0, &priv->phy);
#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_plat(struct udevice *dev)
static int rk3188_dmc_probe(struct udevice *dev)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct rk3188_sdram_params *plat = dev_get_plat(dev);
struct regmap *map;
struct udevice *dev_clk;
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_plat(dev);
if (ret)
.id = UCLASS_RAM,
.of_match = rk3188_dmc_ids,
.ops = &rk3188_dmc_ops,
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.of_to_plat = rk3188_dmc_of_to_plat,
#endif
.probe = rk3188_dmc_probe,
.priv_auto = sizeof(struct dram_info),
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.plat_auto = sizeof(struct rk3188_sdram_params),
#endif
};
#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
{
int i;
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int conv_of_plat(struct udevice *dev)
static int rk3288_dmc_probe(struct udevice *dev)
{
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
struct rk3288_sdram_params *plat = dev_get_plat(dev);
struct udevice *dev_clk;
struct regmap *map;
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
#if CONFIG_IS_ENABLED(OF_PLATDATA)
ret = conv_of_plat(dev);
if (ret)
.of_match = rk3288_dmc_ids,
.ops = &rk3288_dmc_ops,
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.of_to_plat = rk3288_dmc_of_to_plat,
#endif
.probe = rk3288_dmc_probe,
.priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.plat_auto = sizeof(struct rk3288_sdram_params),
#endif
};
.probe = rk3399_dmc_probe,
.priv_auto = sizeof(struct dram_info),
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
.plat_auto = sizeof(struct rockchip_dmc_plat),
#endif
};
struct dram_info {
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
void __iomem *pctl;
void __iomem *phy;
struct rv1126_cru *cru;
};
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
#define GRF_BASE_ADDR 0xfe000000
#define PMU_GRF_BASE_ADDR 0xfe020000
static int rv1126_dmc_probe(struct udevice *dev)
{
#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
if (rv1126_dmc_init(dev))
return 0;
#else
u32 *physical_filter_ctrl;
};
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
struct sifive_ddr_params {
struct sifive_ddrctl pctl_regs;
struct sifive_ddrphy phy_regs;
priv->info.base = gd->ram_base;
priv->info.size = gd->ram_size;
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
int ret;
u32 clock = 0;
.ops = &sifive_ddr_ops,
.probe = sifive_ddr_probe,
.priv_auto = sizeof(struct sifive_ddr_info),
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
.plat_auto = sizeof(struct sifive_dmc_plat),
#endif
};
#
# Copyright (c) 2022 StarFive, Inc
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_start.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_train.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += starfive_ddr.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrphy_utils.o
obj-$(CONFIG_SPL_STARFIVE_DDR) += ddrcsr_boot.o
-endif
\ No newline at end of file
+endif
priv->info.base = STM32_DDR_BASE;
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
priv->info.size = 0;
ret = stm32mp1_ddr_setup(dev);
*/
static bool socfpga_reset_keep_enabled(void)
{
-#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
+#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
const char *env_str;
long val;
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
ifdef CONFIG_SCSI
obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o
endif
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_SPL_SATA
obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o
endif
obj-$(CONFIG_XTENSA_SEMIHOSTING_SERIAL) += serial_xtensa_semihosting.o
obj-$(CONFIG_S5P4418_PL011_SERIAL) += serial_s5p4418_pl011.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
endif
obj-$(CONFIG_UART4_SERIAL) += serial_adi_uart4.o
.setbrg = atmel_serial_setbrg,
};
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
+#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_SPL_CLK)
static int atmel_serial_enable_clk(struct udevice *dev)
{
struct atmel_serial_priv *priv = dev_get_priv(dev);
void ns16550_init(struct ns16550 *com_port, int baud_divisor)
{
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_OMAP34XX)
/*
* On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
* before SPL starts only THRE bit is set. We have to empty the
char ns16550_getc(struct ns16550 *com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_TTY)
extern void usbtty_poll(void);
usbtty_poll();
#endif
}
}
}
- if (!IS_ENABLED(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(OF_CONTROL) ||
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(OF_CONTROL) ||
!blob) {
/*
* Try to use CONFIG_CONS_INDEX if available (it is numbered
/* We must have a console device */
if (!dev) {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
puts("Cannot find console\n");
hang();
#else
writeb(val % 16, &uart->rest.value);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int s5p_serial_setbrg(struct udevice *dev, int baudrate)
{
struct s5p_serial_plat *plat = dev_get_plat(dev);
return 0;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
static int zynq_serial_setconfig(struct udevice *dev, uint serial_config)
{
struct zynq_uart_plat *plat = dev_get_plat(dev);
static int request_gpio_cs(struct udevice *bus)
{
-#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_XPL_BUILD)
struct dw_spi_priv *priv = dev_get_priv(bus);
int ret;
*/
__weak void external_cs_manage(struct udevice *dev, bool on)
{
-#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_XPL_BUILD)
struct dw_spi_priv *priv = dev_get_priv(dev->parent);
if (!dm_gpio_is_valid(&priv->cs_gpio))
sfc->regbase = dev_read_addr_ptr(bus);
sfc->use_dma = !dev_read_bool(bus, "rockchip,sfc-no-dma");
- if (IS_ENABLED(CONFIG_SPL_BUILD) && sfc->use_dma)
+ if (IS_ENABLED(CONFIG_XPL_BUILD) && sfc->use_dma)
sfc->use_dma = !dev_read_bool(bus, "u-boot,spl-sfc-no-dma");
#if CONFIG_IS_ENABLED(CLK)
return -EPROTONOSUPPORT;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
ret = wdt_expire_now(wdt, reset_mode);
if (ret) {
debug("Sysreset failed: %d", ret);
dr_mode = best_dr_mode;
-#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_USB_HOST) || !defined(CONFIG_XPL_BUILD)
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
ret = cdns3_host_init(cdns);
if (ret) {
switch (dr_mode) {
#if defined(CONFIG_SPL_USB_HOST) || \
- (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
+ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
case USB_DR_MODE_HOST:
debug("%s: dr_mode: HOST\n", __func__);
driver = "cdns-usb3-host";
#endif
#if defined(CONFIG_SPL_USB_HOST) || \
- (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
+ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
static int cdns3_host_probe(struct udevice *dev)
{
struct cdns3_host_priv *priv = dev_get_priv(dev);
obj-$(CONFIG_$(SPL_TPL_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o
obj-$(CONFIG_$(SPL_TPL_)USB_ETH_RNDIS) += rndis.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
obj-$(CONFIG_SPL_DFU) += f_dfu.o
obj-$(CONFIG_SPL_USB_SDP_SUPPORT) += f_sdp.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o
obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
obj-$(CONFIG_DFU_OVER_USB) += f_dfu.o
return;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
env_set_hex("filesize", sdp->dnl_bytes);
#endif
printf("done\n");
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static ulong sdp_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
/* If imx header fails, try some U-Boot specific headers */
if (status) {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER))
sdp_func->jmp_address = (u32)search_container_header((ulong)sdp_func->jmp_address, sdp_func->dnl_bytes);
else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT))
}
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int sdp_handle(struct udevice *udc)
#else
int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image,
schedule();
dm_usb_gadget_handle_interrupts(udc);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
flag = sdp_handle_in_ep(spl_image, bootdev);
#else
flag = sdp_handle_in_ep(NULL, NULL);
#endif
#if defined(CONFIG_SPL_USB_HOST) || \
- (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
+ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
static int mtu3_host_probe(struct udevice *dev)
{
struct ssusb_mtk *ssusb = dev_to_ssusb(dev->parent);
#endif
#if defined(CONFIG_SPL_USB_HOST) || \
- (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST))
+ (!defined(CONFIG_XPL_BUILD) && defined(CONFIG_USB_HOST))
case USB_DR_MODE_HOST:
dev_dbg(parent, "%s: dr_mode: host\n", __func__);
driver = "mtu3-host";
projects / u-boot.git / commitdiff
