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riscv: andes_plicsw: Fix IPI during OpenSBI invocation
authorYu Chien Peter Lin <peterlin@andestech.com>
Tue, 4 Jul 2023 11:13:20 +0000 (19:13 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Thu, 6 Jul 2023 09:28:08 +0000 (17:28 +0800)
commitbc35b49a5c12891d969e28dbf29024ca664dea8b
tree9b3ef41d80f6bdc93586996f987597035fe2d0eatree | snapshot
parent9eb0fc24c9804118e44b70851b1ad03aa1fc8cd4commit | diff
riscv: andes_plicsw: Fix IPI during OpenSBI invocation

On some AE350 boards, we need to explicitly initialize the priority
registers to a non-zero value so the boot hart can instruct secondary
harts to jump to OpenSBI.

This patch also updates the information about PLICSW.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/lib/andes_plicsw.c diff | blob | history
My U-Boot fork