From cd3c67692b13fb24f69b3016bc9990eeaaa32ca1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Fri, 5 Jun 2015 14:39:37 -0600
Subject: [PATCH] tegra: clock: Adjust PLL access to avoid a warning
A harmless but confusing warning is displayed when looking up the
DisplayPort PLL. Correct this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
---
arch/arm/mach-tegra/clock.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 590826072b..24047b8c82 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -84,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
assert(clock_id_is_pll(clkid));
if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
- debug("%s: Invalid PLL\n", __func__);
+ debug("%s: Invalid PLL %d\n", __func__, clkid);
return NULL;
}
return &clkrst->crc_pll[clkid];
@@ -120,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
- struct clk_pll *pll = get_pll(clkid);
+ struct clk_pll *pll = NULL;
u32 misc_data, data;
+ if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
+ pll = get_pll(clkid);
+
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
--
2.39.5