From bd1bb3c6a7364145fd781aeef56fa661e918f707 Mon Sep 17 00:00:00 2001 From: Heiko Schocher <hs@denx.de> Date: Fri, 31 Oct 2014 08:30:59 +0100 Subject: [PATCH] arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas BieÃmann <andreas.devel@googlemail.com> --- arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h index 5741f6e94a..130a85abee 100644 --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address, #define ATMEL_MPDDRC_CR_DIC_DS (0x1 << 8) #define ATMEL_MPDDRC_CR_DIS_DLL (0x1 << 9) #define ATMEL_MPDDRC_CR_OCD_DEFAULT (0x7 << 12) +#define ATMEL_MPDDRC_CR_DQMS_SHARED (0x1 << 16) #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 << 17) #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 << 20) #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 << 21) -- 2.39.5