From 7afc45ad7d9493208d89072cbb78a5bfc8034b59 Mon Sep 17 00:00:00 2001 From: Kumar Gala <galak@kernel.crashing.org> Date: Sun, 13 Mar 2011 10:55:53 -0500 Subject: [PATCH] powerpc/85xx: Fix synchronization of timebase on MP boot There is a small ordering issue in the master core in that we need to make sure the disabling of the timebase in the SoC is visible before we set the value to 0. We can simply just read back the value to synchronizatize the write, before we set TB to 0. Reported-by: Dan Hettena Tested-by: Dan Hettena Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/mp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 6c0da83176..758e6d7045 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -276,8 +276,13 @@ static void plat_mp_up(unsigned long bootpg) /* enable time base at the platform */ out_be32(&rcpm->ctbenrl, 0); + + /* readback to sync write */ + in_be32(&rcpm->ctbenrl); + mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); + out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1); #ifdef CONFIG_MPC8xxx_DISABLE_BPTR @@ -347,6 +352,10 @@ static void plat_mp_up(unsigned long bootpg) else devdisr |= MPC85xx_DEVDISR_TB0; out_be32(&gur->devdisr, devdisr); + + /* readback to sync write */ + in_be32(&gur->devdisr); + mtspr(SPRN_TBWU, 0); mtspr(SPRN_TBWL, 0); -- 2.39.5