From 6ce83fb3d6ac1cd25772b3c8c1265afbfa42f718 Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Date: Tue, 12 Sep 2017 19:56:41 +0200
Subject: [PATCH] FSL PCI: Configure PCIe reference ratio
Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.
This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.
Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
drivers/pci/fsl_pci_init.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 375b8549c5..b4c8556686 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -321,6 +321,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
pci_setup_indirect(hose, cfg_addr, cfg_data);
+#ifdef PEX_CCB_DIV
+ /* Configure the PCIE controller core clock ratio */
+ pci_hose_write_config_dword(hose, dev, 0x440,
+ ((gd->bus_clk / 1000000) *
+ (16 / PEX_CCB_DIV)) / 333);
+#endif
block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */
--
2.39.5