From 39b18c4f3e0b6d0dc00f4e68bad2da3766c85f09 Mon Sep 17 00:00:00 2001 From: "ebony.zhu@freescale.com" <ebony.zhu@freescale.com> Date: Mon, 18 Dec 2006 16:25:15 +0800 Subject: [PATCH] u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default This patch disables MPC8548CDS 2T_TIMING for DDR by default. Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com> --- include/configs/MPC8548CDS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bfd316cb94..687fe84850 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -41,7 +41,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ +#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -- 2.39.5