From: Anand Moon <linux.amoon@gmail.com>
Date: Sat, 5 Jun 2021 14:38:43 +0000 (+0000)
Subject: pci: pcie_dw_rockchip: Replace msleep occurences by udelay
X-Git-Tag: v2025.01-rc5-pxa1908~1819^2~8^2~3
X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-favicon.png?a=commitdiff_plain;h=88647f078dbae9a43a37af37454f2b9f535a16dd;p=u-boot.git

pci: pcie_dw_rockchip: Replace msleep occurences by udelay

Replace msleep occurences by udelay.

drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
     declaration of function 'msleep' [-Wimplicit-function-declaration]

Cc: Patrick Wildt <patrick@blueri.se>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 4e448c0a3d..9322e735b9 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -61,7 +61,7 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBF_EN		0xffff0003
 
 /* Parameters for the waiting for #perst signal */
-#define PERST_WAIT_MS			1000
+#define MACRO_US			1000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
@@ -249,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		 * some wired devices need much more, such as 600ms.
 		 * Add a enough delay to cover all cases.
 		 */
-		msleep(PERST_WAIT_MS);
+		udelay(MACRO_US * 1000);
 		dm_gpio_set_value(&priv->rst_gpio, 1);
 	}
 
@@ -271,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 			 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
 		rk_pcie_debug_dump(priv);
-		msleep(1000);
+		udelay(MACRO_US * 1000);
 	}
 
 	dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
 	/* Link maybe in Gen switch recovery but we need to wait more 1s */
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 	return -EIO;
 }
 
@@ -296,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		}
 	}
 
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 
 	ret = generic_phy_init(&priv->phy);
 	if (ret) {