From: Pankaj Bansal <pankaj.bansal@nxp.com>
Date: Mon, 14 Oct 2019 11:43:19 +0000 (+0000)
Subject: pci: layerscape: Only set EP CFG READY bit
X-Git-Tag: v2025.01-rc5-pxa1908~2700^2~16
X-Git-Url: http://git.dujemihanovic.xyz/html/static/git-favicon.png?a=commitdiff_plain;h=05c81d98e4f3587180d26068b5925a08f3880dd2;p=u-boot.git

pci: layerscape: Only set EP CFG READY bit

In ls_pcie_ep_enable_cfg(), as part of EP setup,config ready bit
of pci controller is set, so that RC can read the config space of EP.

While setting the config ready bit, LTSSM_EN bit in same register was
also inadvertently getting cleared. This restarts the link training
between RC and EP.

Update code to just set the desired CFG_READY bit (bit 0),
while leaving the other bits unchanged.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index db1375a1ce..5ad7c28773 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -406,7 +406,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
 
 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
 {
-	ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+	u32 config;
+
+	config = ctrl_readl(pcie,  PCIE_PF_CONFIG);
+	config |= PCIE_CONFIG_READY;
+	ctrl_writel(pcie, config, PCIE_PF_CONFIG);
 }
 
 static void ls_pcie_setup_ep(struct ls_pcie *pcie)