arm: dts: imx6qdl-icore-rqs: Add FEC node

Add FEC node for Engicam i.CoreM6 RQS modules.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
index 2aaa6e4a87d47f2da51fe167863e73723b92193c..750229bab5e3502f0e4b707fdcde5fa0bf0d4394 100644 (file)
--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -48,6 +48,31 @@
        };
 };
 
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet>;
+       phy-handle = <&eth_phy>;
+       phy-mode = "rgmii";
+       status = "okay";
+
+       mdio {
+               eth_phy: ethernet-phy {
+                       rxc-skew-ps = <1140>;
+                       txc-skew-ps = <1140>;
+                       txen-skew-ps = <600>;
+                       rxdv-skew-ps = <240>;
+                       rxd0-skew-ps = <420>;
+                       rxd1-skew-ps = <600>;
+                       rxd2-skew-ps = <420>;
+                       rxd3-skew-ps = <240>;
+                       txd0-skew-ps = <60>;
+                       txd1-skew-ps = <60>;
+                       txd2-skew-ps = <60>;
+                       txd3-skew-ps = <240>;
+               };
+       };
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -83,6 +108,27 @@
 };
 
 &iomuxc {
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1