This is the initial support for Broadcom's ARM-based 47622 SOC.
In this change, our first SOC is an armv7 platform called 47622. The
initial support includes a bare-bone implementation and dts with ARM
PL011 uart.
The SOC-specific code resides in arch/arm/mach-bcmbca/<soc> and board
related code is in board/broadcom/bcmba.
The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Kursad Oney <kursad.oney@broadcom.com>
Signed-off-by: Anand Gore <anand.gore@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
F: configs/rpi_*
T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git
+ARM BROADCOM BCMBCA
+M: Anand Gore <anand.gore@broadcom.com>
+M: William Zhang <william.zhang@broadcom.com>
+M: Kursad Oney <kursad.oney@broadcom.com>
+M: Joel Peshkin <joel.peshkin@broadcom.com>
+S: Maintained
+F: arch/arm/mach-bcmbca/
+F: board/broadcom/bcmbca/
+F: configs/bcm947622_defconfig
+F: include/configs/bcm947622.h
+
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
S: Maintained
This enables support for Broadcom ARM-based set-top box
chipsets, including the 7445 family of chips.
+config ARCH_BCMBCA
+ bool "Broadcom broadband chip family"
+ select DM
+ select OF_CONTROL
+
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
select CPU_V7A
source "arch/arm/mach-bcm283x/Kconfig"
+source "arch/arm/mach-bcmbca/Kconfig"
+
source "arch/arm/mach-bcmstb/Kconfig"
source "arch/arm/mach-davinci/Kconfig"
machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
+machine-$(CONFIG_ARCH_BCMBCA) += bcmbca
machine-$(CONFIG_ARCH_BCMSTB) += bcmstb
machine-$(CONFIG_ARCH_DAVINCI) += davinci
machine-$(CONFIG_ARCH_EXYNOS) += exynos
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
+dtb-$(CONFIG_BCM47622) += \
+ bcm947622.dtb
+
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm47622", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ cpu_off = <1>;
+ cpu_on = <2>;
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x818000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm47622.dtsi"
+
+/ {
+ model = "Broadcom BCM947622 Reference Board";
+ compatible = "brcm,bcm947622", "brcm,bcm47622", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if ARCH_BCMBCA
+
+config BCM47622
+ bool "Support for Broadcom 47622 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+endif
+
+source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+obj-$(CONFIG_BCM47622) += bcm47622/
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM47622
+
+config TARGET_BCM947622
+ bool "Broadcom 47622 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm47622"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+config SYS_BOARD
+ default "bcmbca"
+
+config SYS_VENDOR
+ default "broadcom"
+
+if TARGET_BCM947622
+
+config SYS_CONFIG_NAME
+ default "bcm947622"
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+
+obj-y += board.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ if (fdtdec_setup_mem_size_base() != 0)
+ puts("fdtdec_setup_mem_size_base() has failed\n");
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ fdtdec_setup_memory_banksize();
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM47622=y
+CONFIG_TARGET_BCM947622=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm947622"
+CONFIG_IDENT_STRING=" Broadcom BCM47622"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM947622_H
+#define __BCM947622_H
+
+#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define COUNTER_FREQUENCY 50000000
+#endif
projects / u-boot.git / commitdiff
