arm: socfpga: Add clock manager for Intel N5X device

Add clock manager for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>

diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c
new file mode 100644 (file)
index 0000000..4f09853
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <dm.h>
+#include <dt-bindings/clock/n5x-clock.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+       struct udevice *dev;
+       struct clk clk;
+       ulong rate;
+       int ret;
+
+       ret = uclass_get_device_by_driver(UCLASS_CLK,
+                                         DM_DRIVER_GET(socfpga_n5x_clk),
+                                         &dev);
+       if (ret)
+               return 0;
+
+       clk.id = id;
+       ret = clk_request(dev, &clk);
+       if (ret < 0)
+               return 0;
+
+       rate = clk_get_rate(&clk);
+
+       clk_free(&clk);
+
+       if ((rate == (unsigned long)-ENXIO) ||
+           (rate == (unsigned long)-EIO)) {
+               debug("%s id %u: clk_get_rate err: %ld\n",
+                     __func__, id, rate);
+               return 0;
+       }
+
+       return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+       return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+       return cm_get_rate_dm(N5X_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+       return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+       printf("MPU       %10d kHz\n",
+              cm_get_rate_dm_khz(N5X_MPU_CLK));
+       printf("L4 Main     %8d kHz\n",
+              cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
+       printf("L4 sys free %8d kHz\n",
+              cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
+       printf("L4 MP       %8d kHz\n",
+              cm_get_rate_dm_khz(N5X_L4_MP_CLK));
+       printf("L4 SP       %8d kHz\n",
+              cm_get_rate_dm_khz(N5X_L4_SP_CLK));
+       printf("SDMMC       %8d kHz\n",
+              cm_get_rate_dm_khz(N5X_SDMMC_CLK));
+}

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30ec5131f1b565024ea99e96d3b755405..a8cb07a1c47eea365eadeb3ad64075527d195eaa 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #include <asm/arch/clock_manager_s10.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #include <asm/arch/clock_manager_agilex.h>
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include <asm/arch/clock_manager_n5x.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */

diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644 (file)
index 0000000..54615ae
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */