]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
board: ti: k3: Remove need for CFG_SYS_SDRAM_BASE
authorAndrew Davis <afd@ti.com>
Thu, 30 Nov 2023 14:49:11 +0000 (08:49 -0600)
committerTom Rini <trini@konsulko.com>
Fri, 15 Dec 2023 20:39:42 +0000 (15:39 -0500)
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.

Signed-off-by: Andrew Davis <afd@ti.com>
board/ti/am65x/evm.c
board/ti/j721e/evm.c
board/ti/j721s2/evm.c
include/configs/am62ax_evm.h
include/configs/am65x_evm.h
include/configs/j721e_evm.h
include/configs/j721s2_evm.h

index 975eb17946f5c6255036e7bbff32c8cdc8b9ffb8..df209021c1b794deb41b6017884fda9c6fa3be4f 100644 (file)
@@ -73,13 +73,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 int dram_init_banksize(void)
 {
        /* Bank 0 declares the memory available in the DDR low region */
-       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].start = 0x80000000;
        gd->bd->bi_dram[0].size = 0x80000000;
        gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
        /* Bank 1 declares the memory available in the DDR high region */
-       gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+       gd->bd->bi_dram[1].start = 0x880000000;
        gd->bd->bi_dram[1].size = 0x80000000;
        gd->ram_size = 0x100000000;
 #endif
index 0768385f40c6b586faeab40070c81204970c5ee7..c541880107ec11ed74fdad63ce626efa0db68429 100644 (file)
@@ -61,13 +61,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 int dram_init_banksize(void)
 {
        /* Bank 0 declares the memory available in the DDR low region */
-       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].start = 0x80000000;
        gd->bd->bi_dram[0].size = 0x80000000;
        gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
        /* Bank 1 declares the memory available in the DDR high region */
-       gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+       gd->bd->bi_dram[1].start = 0x880000000;
        gd->bd->bi_dram[1].size = 0x80000000;
        gd->ram_size = 0x100000000;
 #endif
index db7173907713c7ea01711363fbb5c0891d035a22..1220cd84519bb9bf6cc5da7cbf6d997cdede0a95 100644 (file)
@@ -56,13 +56,13 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 int dram_init_banksize(void)
 {
        /* Bank 0 declares the memory available in the DDR low region */
-       gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
+       gd->bd->bi_dram[0].start = 0x80000000;
        gd->bd->bi_dram[0].size = 0x7fffffff;
        gd->ram_size = 0x80000000;
 
 #ifdef CONFIG_PHYS_64BIT
        /* Bank 1 declares the memory available in the DDR high region */
-       gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE1;
+       gd->bd->bi_dram[1].start = 0x880000000;
        gd->bd->bi_dram[1].size = 0x37fffffff;
        gd->ram_size = 0x400000000;
 #endif
index 57003f120f9affebafce98b4fa80f04754b3bc0a..496d1c2348f9cd2793fa8cc264e1bc0ef55c1d73 100644 (file)
 #include <env/ti/mmc.h>
 #include <env/ti/k3_dfu.h>
 
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1            0x880000000
-
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
index 811dc0ff1a819ac014163463f67a58f791e437ea..64458ebb4b8a3a829ca570dc252733510b985997 100644 (file)
@@ -14,9 +14,6 @@
 #include <env/ti/k3_rproc.h>
 #include <env/ti/k3_dfu.h>
 
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1            0x880000000
-
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
index ea39d1bf8241b0f3adf08a59e113c94fab9410cd..c26438c8684e81a92eaa416a8f759e895b61baf7 100644 (file)
@@ -11,8 +11,6 @@
 
 #include <linux/sizes.h>
 
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1            0x880000000
 /* FLASH Configuration */
 #define CFG_SYS_FLASH_BASE             0x000000000
 
index 692c6bb5e42bd17aa1949faf6cb2e99a4c4cf1de..846cfa7531cc59233edbe7cdd948de9185549363 100644 (file)
@@ -12,9 +12,6 @@
 #include <linux/sizes.h>
 #include <config_distro_bootcmd.h>
 
-/* DDR Configuration */
-#define CFG_SYS_SDRAM_BASE1            0x880000000
-
 /* SPL Loader Configuration */
 #if defined(CONFIG_TARGET_J721S2_A72_EVM)
 #define CFG_SYS_UBOOT_BASE             0x50280000