armv8: lsch3: Add serdes and DDR voltage setup

Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 179cac6e49368690e72b61b2c91eace126ba1b58..9ee0dd23e9c9f915d9449ffac3b5dac477efef4d 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -158,6 +158,293 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
        serdes_prtcl_map[NONE] = 1;
 }
 
+__weak int get_serdes_volt(void)
+{
+       return -1;
+}
+
+__weak int set_serdes_volt(int svdd)
+{
+       return -1;
+}
+
+#define LNAGCR0_RT_RSTB                0x00600000
+
+#define RSTCTL_RESET_MASK      0x000000E0
+
+#define RSTCTL_RSTREQ          0x80000000
+#define RSTCTL_RST_DONE                0x40000000
+#define RSTCTL_RSTERR          0x20000000
+
+#define RSTCTL_SDEN            0x00000020
+#define RSTCTL_SDRST_B         0x00000040
+#define RSTCTL_PLLRST_B                0x00000080
+
+#define TCALCR_CALRST_B                0x08000000
+
+struct serdes_prctl_info {
+       u32 id;
+       u32 mask;
+       u32 shift;
+};
+
+struct serdes_prctl_info srds_prctl_info[] = {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       {.id = 1,
+        .mask = FSL_CHASSIS3_SRDS1_PRTCL_MASK,
+        .shift = FSL_CHASSIS3_SRDS1_PRTCL_SHIFT
+       },
+
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       {.id = 2,
+        .mask = FSL_CHASSIS3_SRDS2_PRTCL_MASK,
+        .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
+       },
+#endif
+       {} /* NULL ENTRY */
+};
+
+static int get_serdes_prctl_info_idx(u32 serdes_id)
+{
+       int pos = 0;
+       struct serdes_prctl_info *srds_info;
+
+       /* loop until NULL ENTRY defined by .id=0 */
+       for (srds_info = srds_prctl_info; srds_info->id != 0;
+            srds_info++, pos++) {
+               if (srds_info->id == serdes_id)
+                       return pos;
+       }
+
+       return -1;
+}
+
+static void do_enabled_lanes_reset(u32 serdes_id, u32 cfg,
+                                  struct ccsr_serdes __iomem *serdes_base,
+                                  bool cmplt)
+{
+       int i, pos;
+       u32 cfg_tmp;
+
+       pos = get_serdes_prctl_info_idx(serdes_id);
+       if (pos == -1) {
+               printf("invalid serdes_id %d\n", serdes_id);
+               return;
+       }
+
+       cfg_tmp = cfg & srds_prctl_info[pos].mask;
+       cfg_tmp >>= srds_prctl_info[pos].shift;
+
+       for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) {
+               if (cmplt)
+                       setbits_le32(&serdes_base->lane[i].gcr0,
+                                    LNAGCR0_RT_RSTB);
+               else
+                       clrbits_le32(&serdes_base->lane[i].gcr0,
+                                    LNAGCR0_RT_RSTB);
+       }
+}
+
+static void do_pll_reset(u32 cfg,
+                        struct ccsr_serdes __iomem *serdes_base)
+{
+       int i;
+
+       for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+               clrbits_le32(&serdes_base->bank[i].rstctl,
+                            RSTCTL_RESET_MASK);
+               udelay(1);
+
+               setbits_le32(&serdes_base->bank[i].rstctl,
+                            RSTCTL_RSTREQ);
+       }
+       udelay(1);
+}
+
+static void do_rx_tx_cal_reset(struct ccsr_serdes __iomem *serdes_base)
+{
+       clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+       clrbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+}
+
+static void do_rx_tx_cal_reset_comp(u32 cfg, int i,
+                                   struct ccsr_serdes __iomem *serdes_base)
+{
+       if (!(cfg == 0x3 && i == 1)) {
+               udelay(1);
+               setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+               setbits_le32(&serdes_base->srdstcalcr, TCALCR_CALRST_B);
+       }
+       udelay(1);
+}
+
+static void do_pll_reset_done(u32 cfg,
+                             struct ccsr_serdes __iomem *serdes_base)
+{
+       int i;
+       u32 reg = 0;
+
+       for (i = 0; i < 2; i++) {
+               reg = in_le32(&serdes_base->bank[i].pllcr0);
+               if (!(cfg & (0x1 << (1 - i))) && ((reg >> 23) & 0x1)) {
+                       setbits_le32(&serdes_base->bank[i].rstctl,
+                                    RSTCTL_RST_DONE);
+               }
+       }
+}
+
+static void do_serdes_enable(u32 cfg,
+                            struct ccsr_serdes __iomem *serdes_base)
+{
+       int i;
+
+       for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+               setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN);
+               udelay(1);
+
+               setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B);
+               udelay(1);
+               /* Take the Rx/Tx calibration out of reset */
+               do_rx_tx_cal_reset_comp(cfg, i, serdes_base);
+       }
+}
+
+static void do_pll_lock(u32 cfg,
+                       struct ccsr_serdes __iomem *serdes_base)
+{
+       int i;
+       u32 reg = 0;
+
+       for (i = 0; i < 2 && !(cfg & (0x1 << (1 - i))); i++) {
+               /* if the PLL is not locked, set RST_ERR */
+               reg = in_le32(&serdes_base->bank[i].pllcr0);
+               if (!((reg >> 23) & 0x1)) {
+                       setbits_le32(&serdes_base->bank[i].rstctl,
+                                    RSTCTL_RSTERR);
+               } else {
+                       udelay(1);
+                       setbits_le32(&serdes_base->bank[i].rstctl,
+                                    RSTCTL_SDRST_B);
+                       udelay(1);
+               }
+       }
+}
+
+int setup_serdes_volt(u32 svdd)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       struct ccsr_serdes __iomem *serdes1_base =
+                       (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+       u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       struct ccsr_serdes __iomem *serdes2_base =
+                       (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+       u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
+#endif
+       u32 cfg_tmp;
+       int svdd_cur, svdd_tar;
+       int ret = 1;
+
+       /* Only support switch SVDD to 900mV */
+       if (svdd != 900)
+               return -EINVAL;
+
+       /* Scale up to the LTC resolution is 1/4096V */
+       svdd = (svdd * 4096) / 1000;
+
+       svdd_tar = svdd;
+       svdd_cur = get_serdes_volt();
+       if (svdd_cur < 0)
+               return -EINVAL;
+
+       debug("%s: current SVDD: %x; target SVDD: %x\n",
+             __func__, svdd_cur, svdd_tar);
+       if (svdd_cur == svdd_tar)
+               return 0;
+
+       /* Put the all enabled lanes in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, false);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
+#endif
+
+       /* Put the all enabled PLL in reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       cfg_tmp = cfg_rcwsrds1 & 0x3;
+       do_pll_reset(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       cfg_tmp = cfg_rcwsrds1 & 0xC;
+       cfg_tmp >>= 2;
+       do_pll_reset(cfg_tmp, serdes2_base);
+#endif
+
+       /* Put the Rx/Tx calibration into reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       do_rx_tx_cal_reset(serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       do_rx_tx_cal_reset(serdes2_base);
+#endif
+
+       ret = set_serdes_volt(svdd);
+       if (ret < 0) {
+               printf("could not change SVDD\n");
+               ret = -1;
+       }
+
+       /* For each PLL that’s not disabled via RCW enable the SERDES */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       cfg_tmp = cfg_rcwsrds1 & 0x3;
+       do_serdes_enable(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       cfg_tmp = cfg_rcwsrds1 & 0xC;
+       cfg_tmp >>= 2;
+       do_serdes_enable(cfg_tmp, serdes2_base);
+#endif
+
+       /* Wait for at at least 625us, ensure the PLLs being reset are locked */
+       udelay(800);
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       cfg_tmp = cfg_rcwsrds1 & 0x3;
+       do_pll_lock(cfg_tmp, serdes1_base);
+#endif
+
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       cfg_tmp = cfg_rcwsrds1 & 0xC;
+       cfg_tmp >>= 2;
+       do_pll_lock(cfg_tmp, serdes2_base);
+#endif
+       /* Take the all enabled lanes out of reset */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
+#endif
+
+       /* For each PLL being reset, and achieved PLL lock set RST_DONE */
+#ifdef CONFIG_SYS_FSL_SRDS_1
+       cfg_tmp = cfg_rcwsrds1 & 0x3;
+       do_pll_reset_done(cfg_tmp, serdes1_base);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+       cfg_tmp = cfg_rcwsrds1 & 0xC;
+       cfg_tmp >>= 2;
+       do_pll_reset_done(cfg_tmp, serdes2_base);
+#endif
+
+       return ret;
+}
+
 void fsl_serdes_init(void)
 {
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index dc4a437344811d210995fd4b08ec7e9756975af8..b9f837d58d3247a796e19b166fad035a1adb9e1e 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -363,6 +363,45 @@ int sata_init(void)
 }
 #endif
 
+/* Get VDD in the unit mV from voltage ID */
+int get_core_volt_from_fuse(void)
+{
+       struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       int vdd;
+       u32 fusesr;
+       u8 vid;
+
+       /* get the voltage ID from fuse status register */
+       fusesr = in_le32(&gur->dcfg_fusesr);
+       debug("%s: fusesr = 0x%x\n", __func__, fusesr);
+       vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
+               FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
+       if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
+               vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
+                       FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
+       }
+       debug("%s: VID = 0x%x\n", __func__, vid);
+       switch (vid) {
+       case 0x00: /* VID isn't supported */
+               vdd = -EINVAL;
+               debug("%s: The VID feature is not supported\n", __func__);
+               break;
+       case 0x08: /* 0.9V silicon */
+               vdd = 900;
+               break;
+       case 0x10: /* 1.0V silicon */
+               vdd = 1000;
+               break;
+       default:  /* Other core voltage */
+               vdd = -EINVAL;
+               debug("%s: The VID(%x) isn't supported\n", __func__, vid);
+               break;
+       }
+       debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
+
+       return vdd;
+}
+
 #elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index 12fd6b8bdf99b9ecc369b42d3ede2c58ec4e271c..9becdf305d979019b0a6504b8d1b2c8c8d9fb759 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -164,6 +164,7 @@ void fsl_rgmii_init(void);
 #ifdef CONFIG_FSL_LSCH2
 const char *serdes_clock_to_string(u32 clock);
 int get_serdes_protocol(void);
+#endif
 #ifdef CONFIG_SYS_HAS_SERDES
 /* Get the volt of SVDD in unit mV */
 int get_serdes_volt(void);
@@ -172,6 +173,5 @@ int set_serdes_volt(int svdd);
 /* The target volt of SVDD in unit mV */
 int setup_serdes_volt(u32 svdd);
 #endif
-#endif
 
 #endif /* __FSL_SERDES_H__ */

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 957e23b02ad59fe2403b772bf355deb6a0f62157..47e8b5a62e50ec9bfde8ef3b1373433c523f470f 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -387,5 +387,39 @@ struct ccsr_reset {
        u32 ip_rev2;                    /* 0xbfc */
 };
 
+struct ccsr_serdes {
+       struct {
+               u32     rstctl; /* Reset Control Register */
+               u32     pllcr0; /* PLL Control Register 0 */
+               u32     pllcr1; /* PLL Control Register 1 */
+               u32     pllcr2; /* PLL Control Register 2 */
+               u32     pllcr3; /* PLL Control Register 3 */
+               u32     pllcr4; /* PLL Control Register 4 */
+               u32     pllcr5; /* PLL Control Register 5 */
+               u8      res[0x20 - 0x1c];
+       } bank[2];
+       u8      res1[0x90 - 0x40];
+       u32     srdstcalcr;     /* TX Calibration Control */
+       u32     srdstcalcr1;    /* TX Calibration Control1 */
+       u8      res2[0xa0 - 0x98];
+       u32     srdsrcalcr;     /* RX Calibration Control */
+       u32     srdsrcalcr1;    /* RX Calibration Control1 */
+       u8      res3[0xb0 - 0xa8];
+       u32     srdsgr0;        /* General Register 0 */
+       u8      res4[0x800 - 0xb4];
+       struct serdes_lane {
+               u32     gcr0;   /* General Control Register 0 */
+               u32     gcr1;   /* General Control Register 1 */
+               u32     gcr2;   /* General Control Register 2 */
+               u32     ssc0;   /* Speed Switch Control 0 */
+               u32     rec0;   /* Receive Equalization Control 0 */
+               u32     rec1;   /* Receive Equalization Control 1 */
+               u32     tec0;   /* Transmit Equalization Control 0 */
+               u32     ssc1;   /* Speed Switch Control 1 */
+               u8      res1[0x840 - 0x820];
+       } lane[8];
+       u8 res5[0x19fc - 0xa00];
+};
+
 #endif /*__ASSEMBLY__*/
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 1e65e4e1147719310376a49c253f3d958fb2e5ec..cb760b5b38afc1500c1225bda737a0b02a927ab5 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -121,6 +121,7 @@ struct ccsr_ahci {
 
 #ifdef CONFIG_FSL_LSCH3
 void fsl_lsch3_early_init_f(void);
+int get_core_volt_from_fuse(void);
 #elif defined(CONFIG_FSL_LSCH2)
 void fsl_lsch2_early_init_f(void);
 int setup_chip_volt(void);