#define _ASM_BOOT_MODE_H
#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+#define MAKE_CFGVAL_PRIMARY_BOOT 0xfffffff0
+#define MAKE_CFGVAL_SECONDARY_BOOT 0xffffffff
enum boot_device {
WEIM_NOR_BOOT,
#ifdef CONFIG_MX6
#define IMX6_SRC_GPR10_BMODE BIT(28)
+#define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define IMX6_BMODE_MASK GENMASK(7, 0)
#define IMX6_BMODE_SHIFT 4
#ifdef CONFIG_MX7
#define IMX7_SRC_GPR10_BMODE BIT(28)
+#define IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#endif
/* address translation table */
void boot_mode_apply(unsigned cfg_val)
{
#ifdef CONFIG_MX6
+ const u32 persist_sec = IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT;
const u32 bmode = IMX6_SRC_GPR10_BMODE;
#elif CONFIG_MX7
+ const u32 persist_sec = IMX7_SRC_GPR10_PERSIST_SECONDARY_BOOT;
const u32 bmode = IMX7_SRC_GPR10_BMODE;
#endif
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= bmode;
- else
- reg &= ~bmode;
- writel(reg, &psrc->gpr10);
+ if (cfg_val == MAKE_CFGVAL_PRIMARY_BOOT)
+ clrbits_le32(&psrc->gpr10, persist_sec);
+ else if (cfg_val == MAKE_CFGVAL_SECONDARY_BOOT)
+ setbits_le32(&psrc->gpr10, persist_sec);
+ else {
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= bmode;
+ else
+ reg &= ~bmode;
+ writel(reg, &psrc->gpr10);
+ }
}
#endif
#ifndef CONFIG_SPL_BUILD
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
+ {"primary", MAKE_CFGVAL_PRIMARY_BOOT},
+ {"secondary", MAKE_CFGVAL_SECONDARY_BOOT},
{NULL, 0},
};
#endif