riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"

There is no need for RISCV_NDS_CACHE config to control cache switches.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 4a7295d30c5fd1cf80ee5aae92f43933b0be166b..eca68ea2a7ccf7aee8fb3b0203a94ed4aa2fb72d 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -12,13 +12,3 @@ config RISCV_NDS
        help
          Run U-Boot on AndeStar V5 platforms and use some specific features
          which are provided by Andes Technology AndeStar V5 families.
-
-if RISCV_NDS
-
-config RISCV_NDS_CACHE
-       bool "AndeStar V5 families specific cache support"
-       depends on RISCV_MMODE || SPL_RISCV_MMODE
-       help
-         Provide Andes Technology AndeStar V5 families specific cache support.
-
-endif

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 35f23c748d1b9c939519c8518db7d8eb5851fd87..1c0c3772a115c19a0cf23a8ae64774d2153fe2ea 100644 (file)
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)
 
 void icache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       asm volatile (
-               "csrr t1, mcache_ctl\n\t"
-               "ori t0, t1, 0x1\n\t"
-               "csrw mcache_ctl, t0\n\t"
-       );
-#endif
-#endif
-#endif
 }
 
 void icache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       asm volatile (
-               "fence.i\n\t"
-               "csrr t1, mcache_ctl\n\t"
-               "andi t0, t1, ~0x1\n\t"
-               "csrw mcache_ctl, t0\n\t"
-       );
-#endif
-#endif
-#endif
 }
 
 void dcache_enable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       asm volatile (
-               "csrr t1, mcache_ctl\n\t"
-               "ori t0, t1, 0x2\n\t"
-               "csrw mcache_ctl, t0\n\t"
-       );
-#endif
-#ifdef CONFIG_V5L2_CACHE
-       _cache_enable();
-#endif
-#endif
-#endif
 }
 
 void dcache_disable(void)
 {
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-       asm volatile (
-               "csrr t1, mcache_ctl\n\t"
-               "andi t0, t1, ~0x2\n\t"
-               "csrw mcache_ctl, t0\n\t"
-       );
-#endif
-#ifdef CONFIG_V5L2_CACHE
-       _cache_disable();
-#endif
-#endif
-#endif
 }
 
 int icache_status(void)
 {
-       int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       asm volatile (
-               "csrr t1, mcache_ctl\n\t"
-               "andi   %0, t1, 0x01\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-       );
-#endif
-#endif
-
-       return ret;
+       return 0;
 }
 
 int dcache_status(void)
 {
-       int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-       asm volatile (
-               "csrr t1, mcache_ctl\n\t"
-               "andi   %0, t1, 0x02\n\t"
-               : "=r" (ret)
-               :
-               : "memory"
-       );
-#endif
-#endif
-
-       return ret;
+       return 0;
 }

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 40f41a817c9c16a52a8a412c72328b3190aef7e3..6cb8c3e980c38d12111084c8d9215f6d0735045d 100644 (file)
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -25,7 +25,6 @@ config L2X0_CACHE
 config V5L2_CACHE
        bool "Andes V5L2 cache driver"
        select CACHE
-       depends on RISCV_NDS_CACHE
        help
          Support Andes V5L2 cache controller in AE350 platform.
          It will configure tag and data ram timing control from the