Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
-
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
* configured, and a value of 0 otherwise. These macros are always defined.
*/
-
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
-
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */
-
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
-
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/*----------------------------------------------------------------------
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
-
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
-
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */
-
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
-
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
-
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (1 byte aligned)
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
-
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
* configured, and a value of 0 otherwise. These macros are always defined.
*/
-
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
-
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */
-
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
-
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */
-
/*
* External interrupt vectors/levels.
* These macros describe how Xtensa processor interrupt numbers
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
-
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
/*----------------------------------------------------------------------
DEBUG
----------------------------------------------------------------------*/
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
-
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
.endif
.endm // xchal_ncp_load
-
#define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
#ifndef _XTENSA_CORE_CONFIGURATION_H
#define _XTENSA_CORE_CONFIGURATION_H
-
/****************************************************************************
Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
* configured, and a value of 0 otherwise. These macros are always defined.
*/
-
/*----------------------------------------------------------------------
ISA
----------------------------------------------------------------------*/
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
-
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
-
/*----------------------------------------------------------------------
MISC
----------------------------------------------------------------------*/
#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */
-
/*----------------------------------------------------------------------
CACHE
----------------------------------------------------------------------*/
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
-
/****************************************************************************
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
XCHAL_HAVE_DCACHE_DYN_WAYS) && \
(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
-
/*----------------------------------------------------------------------
INTERNAL I/D RAM/ROMs and XLMI
----------------------------------------------------------------------*/
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
-
/*----------------------------------------------------------------------
INTERRUPTS and TIMERS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 3.) */
-
/*
* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
-
/*----------------------------------------------------------------------
EXCEPTIONS and VECTORS
----------------------------------------------------------------------*/
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
-
/*----------------------------------------------------------------------
DEBUG MODULE
----------------------------------------------------------------------*/
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
-
/*----------------------------------------------------------------------
MMU
----------------------------------------------------------------------*/
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
-
#endif /* _XTENSA_CORE_CONFIGURATION_H */
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
-
/*
* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
.endif
.endm // xchal_ncp_load
-
#define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
loop \at, 99f
.endm
-
.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
.ifgt \incr_log2 - 1
addi \at, \as, (1 << \incr_log2) - 1
loop\cond \at, 99f
.endm
-
.macro __loopt ar, as, at, incr_log2
sub \at, \as, \ar
.ifgt \incr_log2 - 1
loop \at, 99f
.endm
-
.macro __loop as
loop \as, 99f
.endm
-
.macro __endl ar, as
99:
.endm
-
#else
.macro __loopi ar, at, size, incr
98:
.endm
-
.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
.ifnc \mask_log2,
extui \at, \as, \incr_log2, \mask_log2
98:
.endm
-
.macro __loop as
98:
.endm
-
.macro __endl ar, as
bltu \ar, \as, 98b
99:
.endm
-
#endif
-
.macro __endla ar, as, incr
addi \ar, \ar, \incr
__endl \ar \as
.endm
-
#endif /* _XTENSA_ASMMACRO_H */
.endm
-
.macro __loop_cache_range ar as at insn line_width
extui \at, \ar, 0, \line_width
.endm
-
.macro __loop_cache_page ar at insn line_width
__loopi \ar, \at, PAGE_SIZE, 4 << (\line_width)
.endm
-
.macro ___unlock_dcache_all ar at
#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
.endm
-
.macro ___unlock_icache_all ar at
#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
.endm
-
.macro ___flush_invalidate_dcache_all ar at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___flush_dcache_all ar at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_dcache_all ar at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_icache_all ar at
#if XCHAL_ICACHE_SIZE
.endm
-
.macro ___flush_invalidate_dcache_range ar as at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___flush_dcache_range ar as at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_dcache_range ar as at
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_icache_range ar as at
#if XCHAL_ICACHE_SIZE
.endm
-
.macro ___flush_invalidate_dcache_page ar as
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___flush_dcache_page ar as
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_dcache_page ar as
#if XCHAL_DCACHE_SIZE
.endm
-
.macro ___invalidate_icache_page ar as
#if XCHAL_ICACHE_SIZE
# error processor byte order undefined!
#endif
-
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem access
*/
#ifndef _XTENSA_PROCESSOR_H
#define _XTENSA_PROCESSOR_H
-
#endif /* _XTENSA_PROCESSOR_H */
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
-
#endif /* __KERNEL__ */
#endif /* _XTENSA_TYPES_H */
delay_cycles(mhz * lo);
}
-
/*
* Return the elapsed time (ticks) since 'base'.
*/
#endif
}
-
/*
* This function is derived from ARM/PowerPC code (read timebase as long long).
* On Xtensa it just returns the timer value.
projects / u-boot.git / commitdiff
