Restore pcm051_rev3_defconfig config

pcm051_rev3_defconfig config (Phytec Wega board) has been dropped in

    64efd11d ("arm: Remove pcm051 board")

due to expired migration deadlines. Here, pcm051_rev3_defconfig support is
reintroduced.

Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
index 28fd62e2313c76f0222c55bbc1dfe76eab39bedc..b3f21e7f52102e63e6ce555b7679f050d8d1d273 100644 (file)
--- a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -16,6 +16,18 @@
 
        ocp {
                u-boot,dm-pre-reloc;
+
+               l4_wkup@44c00000 {
+                       u-boot,dm-pre-reloc;
+
+                       segment@200000 {
+                               u-boot,dm-pre-reloc;
+
+                               target-module@9000 {
+                                       u-boot,dm-pre-reloc;
+                               };
+                       };
+               };
        };
 };
 

diff --git a/board/phytec/phycore_am335x_r2/Kconfig b/board/phytec/phycore_am335x_r2/Kconfig
index 77055e043c128a327ae3043303af5ed4a9586413..4183c2410e6998a1397447876df434b24499478d 100644 (file)
--- a/board/phytec/phycore_am335x_r2/Kconfig
+++ b/board/phytec/phycore_am335x_r2/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_PHYCORE_AM335X_R2
+if TARGET_PCM051 || TARGET_PHYCORE_AM335X_R2
 
 config SYS_BOARD
        default "phycore_am335x_r2"

diff --git a/board/phytec/phycore_am335x_r2/MAINTAINERS b/board/phytec/phycore_am335x_r2/MAINTAINERS
index 8d02b0e19801e77f4dcfb79722cc9e8589671b5b..28c69cb1a837308e1c8346fcc4e0b6c433a928d6 100644 (file)
--- a/board/phytec/phycore_am335x_r2/MAINTAINERS
+++ b/board/phytec/phycore_am335x_r2/MAINTAINERS
@@ -9,3 +9,8 @@ F:      board/phytec/phycore_am335x_r2
 F:     include/configs/phycore_am335x_r2.h
 F:     configs/phycore-am335x-r2-regor_defconfig
 F:     configs/phycore-am335x-r2-wega_defconfig
+
+phyCORE AM335x R3 WEGA BOARD
+M:     Matwey V. Kornilov <matwey.kornilov@gmail.com>
+S:     Maintained
+F:     configs/pcm051_rev3_defconfig

diff --git a/board/phytec/phycore_am335x_r2/board.c b/board/phytec/phycore_am335x_r2/board.c
index 5ca94152049f742e3ca01562f268e295e54b886b..d97ebd015120f60e44521cf0b2df376023a20504 100644 (file)
--- a/board/phytec/phycore_am335x_r2/board.c
+++ b/board/phytec/phycore_am335x_r2/board.c
@@ -31,7 +31,11 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 
 /* DDR RAM defines */
+#if defined(CONFIG_TARGET_PCM051)
+#define DDR_CLK_MHZ            303 /* DDR_DPLL_MULT value */
+#else
 #define DDR_CLK_MHZ            400 /* DDR_DPLL_MULT value */
+#endif
 
 #define OSC    (V_OSCK / 1000000)
 const struct dpll_params dpll_ddr = {
@@ -65,6 +69,7 @@ enum {
        PHYCORE_R2_MT41K128M16JT_256MB,
        PHYCORE_R2_MT41K256M16TW107IT_512MB,
        PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+       PHYCORE_R13_MT41K256M16HA125E_256MB,
 };
 
 struct am335x_sdram_timings {
@@ -127,10 +132,30 @@ static struct am335x_sdram_timings physom_timings[] = {
                        .datawrsratio0 = 0x82,
                },
        },
+       [PHYCORE_R13_MT41K256M16HA125E_256MB] = {
+               .ddr3_emif_reg_data = {
+                       .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+                       .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+                       .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+                       .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+                       .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+                       .zq_config = MT41K256M16HA125E_ZQ_CFG,
+                       .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN,
+               },
+               .ddr3_data = {
+                       .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+                       .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+                       .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+                       .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+               },
+       },
 };
 
 void sdram_init(void)
 {
+#if defined(CONFIG_TARGET_PCM051)
+       int ram_type_index = PHYCORE_R13_MT41K256M16HA125E_256MB;
+#else
        /* Configure memory to maximum supported size for detection */
        int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
 
@@ -157,6 +182,7 @@ void sdram_init(void)
                ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
                break;
        }
+#endif
        config_ddr(DDR_CLK_MHZ, &ioregs,
                   &physom_timings[ram_type_index].ddr3_data,
                   &ddr3_cmd_ctrl_data,

diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig
new file mode 100644 (file)
index 0000000..624113d
--- /dev/null
+++ b/configs/pcm051_rev3_defconfig
@@ -0,0 +1,69 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
+CONFIG_AM33XX=y
+CONFIG_TARGET_PCM051=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4030ff00
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
+CONFIG_SPL_I2C=y
+# CONFIG_SPL_NAND_SUPPORT is not set
+CONFIG_SPL_POWER=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_SPL=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_CLK_TI_CTRL=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHY_SMSC=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETHER=y