config ARM64
bool
select PHYS_64BIT
+ select SYS_CACHE_SHIFT_6
config DMA_ADDR_T_64BIT
bool
config CPU_ARM720T
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM920T
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM926EJS
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM946ES
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM1136
bool
+ select SYS_CACHE_SHIFT_5
config CPU_ARM1176
bool
select HAS_VBAR
+ select SYS_CACHE_SHIFT_5
config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2
+ select SYS_CACHE_SHIFT_6
config CPU_V7M
bool
select HAS_THUMB2
+ select SYS_CACHE_SHIFT_5
config CPU_PXA
bool
+ select SYS_CACHE_SHIFT_5
config CPU_SA1100
bool
+ select SYS_CACHE_SHIFT_5
config SYS_CPU
default "arm720t" if CPU_ARM720T
default 4 if CPU_SA1100
default 8 if ARM64
+config SYS_CACHE_SHIFT_5
+ bool
+
+config SYS_CACHE_SHIFT_6
+ bool
+
+config SYS_CACHE_SHIFT_7
+ bool
+
+config SYS_CACHELINE_SIZE
+ int
+ default 128 if SYS_CACHE_SHIFT_7
+ default 64 if SYS_CACHE_SHIFT_6
+ default 32 if SYS_CACHE_SHIFT_5
+
config SEMIHOSTING
bool "support boot from semihosting"
help
bool "Support ThunderX 88xx"
select ARM64
select OF_CONTROL
+ select SYS_CACHE_SHIFT_7
endchoice
}
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
#include <common.h>
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
void invalidate_dcache_all(void)
{
/* Flush/Invalidate I cache */
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
-/* default Dcache Line length for armada100 */
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 64
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
#define _ASM_ARMV7_LS102XA_CONFIG_
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define OCRAM_BASE_ADDR 0x10000000
#define OCRAM_SIZE 0x00010000
#define OCRAM_BASE_S_ADDR 0x10010000
#define ARCH_MXC
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IPU_SOC_BASE_ADDR 0x40000000
#define ARCH_MXC
-#ifdef CONFIG_MX6UL
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#define ARCH_MXC
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define ROM_SW_INFO_ADDR 0x000001E8
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x00017FFF
#endif
/*
- * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
- * use that value for aligning DMA buffers unless the board config has specified
- * an alternate cache line size.
+ * The value of the largest data cache relevant to DMA operations shall be set
+ * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger
+ * value than found in the L1 cache but this is OK to use in terms of
+ * alignment.
*/
-#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 64
-#endif
#endif /* _ASM_CACHE_H */
#include <common.h>
#include <malloc.h>
-#ifndef CONFIG_SYS_CACHELINE_SIZE
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
/*
* Flush range from all levels of d-cache/unified-cache.
* Affects the range [start, start + size - 1].
#endif /* CONFIG_KW88F6281 */
#include <asm/arch/soc.h>
-#define CONFIG_SYS_CACHELINE_SIZE 32
- /* default Dcache Line length for kirkwood */
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define MV88F78X60 /* for the DDR training bin_hdr code */
#endif
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_L2_PL310
#ifdef CONFIG_SPL_BUILD
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
+ select SYS_CACHE_SHIFT_7
default y
help
This option allows to use the UniPhier System Cache as L2 cache.
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
#include <asm/hardware.h>
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */
/* Commands */
#define CONFIG_FAT_WRITE
-#define CONFIG_SYS_CACHELINE_SIZE 64
#undef CONFIG_USB_GADGET_VBUS_DRAW
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBID_ADDR 0x34052c46
/* Commands */
#define CONFIG_FAT_WRITE
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USBID_ADDR 0x34052c46
#endif /* __BCM28155_AP_H */
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* Memory configuration
* (these must be defined elsewhere)
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
* Although the default iss 64, we still define it
* to be on the safe side once the default is changed.
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
/* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Since SPL did pll and ddr initialization for us,
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
#define CONFIG_SYS_NO_FLASH
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/* USB Host Support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_VF
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000)
#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16MB max kernel size */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* UART */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOARD_COMMON
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_REVISION_TAG
/* SD/MMC configuration */
#include "exynos-common.h"
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_EXYNOS_SPL
#ifdef FTRACE
#define CONFIG_MX35
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_SUPPORT_RAW_INITRD
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_IDENT_STRING "hikey"
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
-#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* Platform
#undef DEBUG
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SH73A0
#define CONFIG_KZM_A9_GT
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
#define CONFIG_MACH_TYPE MACH_TYPE_MCX
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_CPU_ARMV8
#define CONFIG_REMAKE_ELF
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_IS_NOWHERE 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
#define CONFIG_OMAP3_SPI
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
#define CONFIG_OMAP3_SPI
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_OMAP3_ID_NAND
/* Uncomment to define the board revision statically */
/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x40200800
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
-#define CONFIG_SYS_CACHELINE_SIZE 64
/* TWL4030 */
#define CONFIG_TWL4030_PWM
/* Initial RAM setup */
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
-#define CONFIG_SYS_CACHELINE_SIZE 64
/* NAND boot config */
#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#endif /* __CONFIG_H */
#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#ifdef CONFIG_CMD_NET
/* Ethernet (LAN9211 from SMSC9118 family) */
#define CONFIG_SMC911X
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
#ifndef __RCAR_GEN2_COMMON_H
#define __RCAR_GEN2_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/rmobile.h>
#define CONFIG_CMD_DFL
#ifndef __CONFIG_RK3036_COMMON_H
#define __CONFIG_RK3036_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_RK3288_COMMON_H
#define __CONFIG_RK3288_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/hardware.h>
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_RK3399_COMMON_H
#define __CONFIG_RK3399_COMMON_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-#ifdef CONFIG_BCM2835
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#endif
-
/* Architecture, CPU, etc.*/
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_S5PC110 1 /* which is in a S5PC110 */
#define CONFIG_MACH_GONI 1 /* working with Goni */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <linux/sizes.h>
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8998
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* commands to include */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-
-#define CONFIG_SYS_CACHELINE_SIZE 0x2000
#endif
/* General Boot Parameter */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
* (easy to change)
* CPU
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_ARM_ARCH_CP15_ERRATA
#define CONFIG_ARM_ERRATA_454179
#define CONFIG_ARM_ERRATA_430973
/*
* Cache
*/
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* CPU */
#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_TIMER_CLK_FREQ 24000000
/*
#define CONFIG_SYS_TEXT_BASE 0x80008000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* High Level Configuration Options
*/
#define CONFIG_DFU_NAND
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
-
-#define CONFIG_SYS_CACHELINE_SIZE SZ_8K
#endif
/* SPI EEPROM */
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
#include "tegra-common.h"
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
#include "tegra-common.h"
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/*
* Errata configuration
*/
#include "tegra-common.h"
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/*
* NS16550 Configuration
*/
#define _TEGRA30_COMMON_H_
#include "tegra-common.h"
-/* Cortex-A9 uses a cache line size of 32 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
/*
* Errata configuration
*/
#ifndef __CONFIG_TI814X_EVM_H
#define __CONFIG_TI814X_EVM_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_TI81XX
#define CONFIG_TI814X
#define CONFIG_SYS_NO_FLASH
#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH
#define CONFIG_AM33XX
#define CONFIG_ARCH_CPU_INIT
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#define CONFIG_USB_STORAGE
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
-#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
* High Level Configuration Options
*/
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000
#endif
-#define CONFIG_SYS_CACHELINE_SIZE 32
/* Get CPU defs */
#include <asm/arch/cpu.h>
/* Common ARM Erratas */
#define CONFIG_ARM_ERRATA_798870
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
/* #define CONFIG_SYS_ICACHE_OFF */
/* #define CONFIG_SYS_DCACHE_OFF */
-#ifdef CONFIG_CACHE_UNIPHIER
-#define CONFIG_SYS_CACHELINE_SIZE 128
-#else
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#endif
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MISC_INIT_F
#define CONFIG_SUPPORT_RAW_INITRD
-/* MMU Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_IDENT_STRING " vexpress_aemv8a"
/* Link Definitions */
#define CONFIG_SYS_MEMTEST_START V2M_BASE
#define CONFIG_SYS_MEMTEST_END 0x20000000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_SYS_L2CACHE_OFF 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#include <asm/arch/imx-regs.h>
#define CONFIG_VF610
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_DISPLAY_CPUINFO
/* Have release address at the end of 256MB for now */
#define CPU_RELEASE_ADDR 0xFFFFFF0
-/* Cache Definitions */
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
#if !defined(CONFIG_IDENT_STRING)
# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#endif
#endif
/* Cache options */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
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