From c44bb3a30f5a1332176edce1a91c0e2cf666ee8f Mon Sep 17 00:00:00 2001 From: Stephen Warren <swarren@nvidia.com> Date: Tue, 26 Feb 2013 12:28:28 +0000 Subject: [PATCH] ARM: tegra: enable some CPU errata workarounds Tegra20 has a Cortex A9 r1p1, and Tegra30 has a Cortex A9 r2p9. As such, some CPU errata exist, and must be worked around. These must be worked around in the bootloader, since in general, the kernel (especially a multi-platform kernel) needs to support being launched in non-secure mode (normal world), and hence may not be able to write to the CP15 register to enable these workarounds. Signed-off-by: Stephen Warren <swarren@nvidia.com> --- include/configs/tegra20-common.h | 6 ++++++ include/configs/tegra30-common.h | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 33e5f524f1..186e023364 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -25,6 +25,12 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* + * Errata configuration + */ +#define CONFIG_ARM_ERRATA_742230 +#define CONFIG_ARM_ERRATA_751472 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 04517e1409..f6c07c6ecc 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -25,6 +25,12 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* + * Errata configuration + */ +#define CONFIG_ARM_ERRATA_743622 +#define CONFIG_ARM_ERRATA_751472 + /* * NS16550 Configuration */ -- 2.39.5