Caleb Connolly [Thu, 18 Apr 2024 17:25:51 +0000 (18:25 +0100)]
qcom_defconfig: define safe default SYS_LOAD_ADDR
Defining this as 0 results in bootm causing a null pointer exception...
Define it at a safe default which is valid RAM on most qcom boards.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:50 +0000 (18:25 +0100)]
qcom_defconfig: enable OF_BOARD_SETUP
Use our new ft_board_setup().
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:49 +0000 (18:25 +0100)]
mach-snapdragon: implement ft_board_setup() for USB role selection
Some Qualcomm boards have only one USB controller which is muxed between
the type-c port and an internal USB hub for type-A and ethernet. We
modify the DT for these to force them to host mode in U-Boot. However in
Linux DRD role switching is supported (required, even). Use
ft_board_setup() to adjust the dr_mode property for these boards.
While we're here, define pr_fmt for this file so we can more easily
identify log messages.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:48 +0000 (18:25 +0100)]
arm: dts: qrb4210-rb2-u-boot: add u-boot fixups
Add a fixup to force dr_mode to host for U-Boot.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:47 +0000 (18:25 +0100)]
phy: qcom: snps-femto-v2: drop clocks
There is a clock associated with this phy, but it's always from the
rpmhcc and isn't actually needed for the hardware to work.
Drop all the clock handling from the driver.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:46 +0000 (18:25 +0100)]
iommu: qcom-smmu: add qcom generic compatible
With the exception of SDM845, most other Qualcomm SoCs have the Qualcomm
specific (but not SoC) specific SMMU compatible string. Add it here so
we can match those without having to add individual SoCs to the list
here.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:45 +0000 (18:25 +0100)]
gpio: qcom_pmic: add pm8150l
This is used for the volume keys on some SM8150/SM8250 devices.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:25:44 +0000 (18:25 +0100)]
gpio: qcom_pmic: add pm6125
As with some other modern PMICs, writing to the GPIOs seems to make the
device reset.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:21:56 +0000 (10:21 +0200)]
spmi: msm: support controller version 7
Add the defines and support for SPMI arbiters version 7,
which can handle up to 1024 peripherals, and can also drive
a secondary bus which is not implemented yet.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:21:55 +0000 (10:21 +0200)]
spmi: msm: handle peripheral ownership
The cnfg registers provides the owner id for each peripheral,
so we can use this id to check if we're allowed to write register
to each peripherals.
Since the v5 can handle more peripherals, add the max_channels to
scan more starting from version 5, make the channel_map store
32bit values and introduce the SPMI_CHANNEL_READ_ONLY flag to
mark a peripheral as read-only.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:21:54 +0000 (10:21 +0200)]
spmi: msm: properly format command
Since version 2, the cmd format has changed, takes helpers
from Linux driver and use a switch/case to handle all
versions in msm_spmi_write/read() command.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:21:53 +0000 (10:21 +0200)]
spmi: msm: fix version 5 support
Properly use ch_offset in msm_spmi_write() reg access.
Fixes: f5a2d6b4b03 ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:38 +0000 (15:24 +0530)]
board: add support for Schneider HMIBSC board
Support for Schneider Electric HMIBSC. Features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates
- Environment protection
- USB based ethernet adaptors
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:37 +0000 (15:24 +0530)]
arm: dts: qcom: Add Schneider HMIBSC board dts
Schneider HMIBSC board dts has already been reviewed upstream on the
linux-arm-msm mailing list. So once it comes through the Linux kernel
release cycle into the U-Boot dts/upstream subtree, a switch to
OF_UPSTREAM can be made. For the time being maintain the U-Boot copy.
Link: https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@linaro.org/
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:36 +0000 (15:24 +0530)]
pinctrl: qcom: apq8016: Add GPIO pinctrl function
Add GPIO pinctrl function to enable driving GPIO pins as output low or
high.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:35 +0000 (15:24 +0530)]
pinctrl: qcom: Add support for driving GPIO pins output
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:34 +0000 (15:24 +0530)]
serial_msm: Enable RS232 flow control
SE HMIBSC board debug console requires RS232 flow control, so enable
corresponding support if RS232 gpios are present.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:33 +0000 (15:24 +0530)]
apq8016: Add support for UART1 clocks and pinmux
SE HMIBSC board uses UART1 as the main debug console, so add
corresponding clocks and pinmux support. Along with that update
instructions to enable clocks for debug UART support.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Fri, 12 Apr 2024 09:54:32 +0000 (15:24 +0530)]
qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow
ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is
loaded as a first stage bootloader. It leads to secondary CPUs bringup
failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's
actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support")
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 22 Apr 2024 11:43:28 +0000 (13:43 +0200)]
pinctrl: qcom: ipq4019: support all pin functions
Currently, IPQ4019 pinctrl driver supports only a very limited number of
pin functions and is not fully DT compatible with Linux pinctrl nodes.
IPQ40xx SoC-s sometimes use different pin function numbers for the same
function depending on the pin number, so for example I2C0 on GPIO58 uses
function number 3 while on GPIO59 it uses function number 2.
So, in order to make the driver compatible with upstream DTS to avoid the
need to patch the pinctrl nodes in U-Boot and support all of the missing
pin functions lets rework the driver based on upstream Linux IPQ4019
pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses
different function numbers pased on the exact pin number.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 22 Apr 2024 11:43:27 +0000 (13:43 +0200)]
pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
If compiled with logging and debug UART support, the following is printed:
serial_msm serial@
78af000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
This is due to the fact that IPQ4019 pinctrl driver is not available prior
to relocation and thus MSM serial will fail probing as pinctrl provider is
not available.
So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 22 Apr 2024 11:43:26 +0000 (13:43 +0200)]
pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 22 Apr 2024 11:43:25 +0000 (13:43 +0200)]
mach-ipq40xx: import GPIO header from mach-snapgradon
Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 22 Apr 2024 11:43:24 +0000 (13:43 +0200)]
pinctrl: qcom: allow selecting with ARCH_IPQ40XX
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Thu, 18 Apr 2024 09:17:00 +0000 (11:17 +0200)]
arm: mach-ipq40xx: dont select SMEM by default
IPQ40xx SoC-s dont have proper SMEM support like more modern Qualcomm
SoC-s so there is no point in selecting the required drivers.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:24:11 +0000 (18:24 +0100)]
qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET
Give us lots of room for the appended FDT.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:24:10 +0000 (18:24 +0100)]
arm: dts: drop qcom dts files
These files are all identical (or older) than those in dts/upstream.
Drop them as we now use upstream DTS files with OF_UPSTREAM.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Thu, 18 Apr 2024 17:24:09 +0000 (18:24 +0100)]
mach-snapdragon: use OF_UPSTREAM
Switch to using upstream DT from dts/upstream.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 15 Apr 2024 15:03:40 +0000 (16:03 +0100)]
serial: msm: calculate bit clock divider
The driver currently requires the bit clock divider be hardcoded in
devicetree (or use the hardcoded default from apq8016).
The bit clock divider is used to derive the baud rate from the core
clock:
baudrate = clk_rate / csr_div
clk_rate is the actual programmed core clock rate which is returned by
clk_set_rate(), and this UART driver only supports a baudrate of 115200.
We can therefore determine the appropriate value for UARTDM_CSR by
iterating over the possible values and finding the one where the
equation above holds true for a baudrate of 115200.
Implement this logic and drop the non-standard DT bindings for this
driver.
Tested on dragonboard410c.
Tested-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 15 Apr 2024 15:03:39 +0000 (16:03 +0100)]
clk/qcom: ipq4019: return valid rate when setting UART clock
clk_set_rate() should return the clock rate that was set. The IPQ4019
clock driver doesn't set any rates yet but it should still return the
expected value so that drivers can work properly.
For a baud rate of 115200 with an expected bit clock divisor of 16, the
clock rate should be
1843200 so return that frequency.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 15 Apr 2024 15:03:38 +0000 (16:03 +0100)]
clk/qcom: apq8016: return valid rate when setting UART clock
The clk_init_uart() helper always returns 0, but we're meant to return a
real clock rate. Given that we hardcode 115200 baud, just return the
clock rate that we set.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 15 Apr 2024 10:49:26 +0000 (12:49 +0200)]
serial: msm_serial: remove .clk_rate from debug UART
MSM serial in DEBUG UART mode is trying to set .clk_rate, but the
msm_serial_data structure does not have such property at all, so lets
remove it as otherwise it will fail compiling.
Fixes: 90023bdfe979 ("serial: msm: add debug UART")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Robert Marko [Mon, 15 Apr 2024 10:49:25 +0000 (12:49 +0200)]
serial: allow selecting MSM debug UART with ARCH_IPQ40XX
Currently, DEBUG_UART_MSM depends on ARCH_SNAPDRAGON only, but IPQ40XX
devices also use the same UART HW so they can also use the debug UART.
So, allow selecting DEBUG_UART_MSM when using ARCH_IPQ40XX as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Fri, 12 Apr 2024 18:10:21 +0000 (20:10 +0200)]
mmc: msm_sdhci: fix vendor_spec_cap0 registers
The addresses were mistakenly swapped. Put them right.
Reported-by: Sumit Garg <sumit.garg@linaro.org>
Fixes: a737d8962cae ("mmc: msm_sdhci: correct vendor_spec_cap0 register for v5")
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 15:02:51 +0000 (17:02 +0200)]
MAINTAINERS: add Qualcomm mailing list
Add the newly created u-boot-qcom mailing list to keep track of Qualcomm
patches.
Additionally, link to the U-Boot Snapdragon custodian tree.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Sumit Garg [Thu, 11 Apr 2024 12:37:26 +0000 (18:07 +0530)]
mach-snapdragon: Allow other board vendors apart from Qcom
Qcom SoCs derived boards can come from various OEMs/ODMs and not just
Qcom itself. So allow CONFIG_SYS_VENDOR to be set correctly
corressponding to the actual board vendor.
Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Thu, 4 Apr 2024 16:46:40 +0000 (18:46 +0200)]
qcom_defconfig: enable SM8550 & SM8650 clock driver
Enable the SM8550 & SM8650 clock driver in the Qualcomm defconfig.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Thu, 4 Apr 2024 16:46:39 +0000 (18:46 +0200)]
clk: qcom: Add SM8650 clock driver
Add the GCC and TCSRCC clock driver for the SM8650 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Thu, 4 Apr 2024 16:46:38 +0000 (18:46 +0200)]
clk: qcom: Add SM8550 clock driver
Add the GCC and TCSRCC clock driver for the SM8550 SoC.
The GCC driver uses the clk-qcom infrastructure to support GDSCs,
Resets and gates. While the TCSRCC is a simpler clock driver which
only supports gates.
The GCC enable and set_rate callbacks contains some tweaks to
setup clocks for Debug UART, SDCard controller and USB.
The TCSRCC gates returns the XO frequency, which is used by the
Synopsys eUSB2 driver to determine the PHY configuration.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:06 +0000 (20:03 +0200)]
dts: sdm845-db845c-u-boot: adjust MMC clocks
Remove the reference to the xo clock which is on the unsupported rpmhcc
clock controller. It isn't needed for MMC functionality.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:05 +0000 (20:03 +0200)]
pinctrl: qcom: sdm845: add special pin names
Adjust sdm845_get_pin_name() to return the correct names for the special
pins. This fixes a non-fatal -ENOSYS error when probing MMC.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:04 +0000 (20:03 +0200)]
clk/qcom: sdm845: enable SDCC2 core clock
Allow setting the clock rate for the SD card core clock. This is
required for SD card support on SDM845 devices.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:03 +0000 (20:03 +0200)]
mmc: msm_sdhci: use a more sensible default clock rate
We currently default to the lowest rate but this actually doesn't work
on most platforms. Default to the HS400 speed instead which is most
common on Qualcomm platforms.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:02 +0000 (20:03 +0200)]
mmc: msm_sdhci: print core version
This is useful for debugging.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:01 +0000 (20:03 +0200)]
mmc: msm_sdhci: use modern DT handling
using fdtdec_* functions is incompatible with OF_LIVE and generally
offers a less friendly interface. Update to use dev_read_* functions
instead.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Tue, 9 Apr 2024 18:03:00 +0000 (20:03 +0200)]
mmc: msm_sdhci: correct vendor_spec_cap0 register for v5
The V4 and V5 controllers have quite varied register layouts. Inherit
the register offsets and naming from the Linux driver. More version
specific offsets can be inherited from Linux as needed.
Fixes: 364c22a ("mmc: msm_sdhci: Add SDCC version 5.0.0 support")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 8 Apr 2024 13:06:52 +0000 (15:06 +0200)]
qcom_defconfig: enable clocks for qcm2290/sm6115/sm8250
Enable three new clock drivers.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 8 Apr 2024 13:06:51 +0000 (15:06 +0200)]
clk/qcom: add driver for sm8250 GCC
Add a clock driver for the SM8250 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 8 Apr 2024 13:06:50 +0000 (15:06 +0200)]
clk/qcom: add driver for sm6115 GCC
Add a driver for the clock controller in the SM6115 SoC, this is used in
the QRB4210 RB2 board.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Mon, 8 Apr 2024 13:06:49 +0000 (15:06 +0200)]
clk/qcom: add driver for qcm2290 GCC
Add a clock driver for the QCM2290 SoC which is used in the QRB2210 RB1
board.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 10 Apr 2024 15:59:45 +0000 (17:59 +0200)]
button: qcom-pmic: add support for pmk8350 button configs
Finally add the entries for the qcom,pmk8350-pwrkey and qcom,pmk8350-resin
found on PMICs used with SM8350 and later SoCs.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 10 Apr 2024 15:59:44 +0000 (17:59 +0200)]
button: qcom-pmic: move node name checks to btn_data struct
Move node name checks to a proper data struct with all information
for the supported subnodes.
Replace the key offset defines with the Linux driver ones.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 10 Apr 2024 15:59:43 +0000 (17:59 +0200)]
gpio: qcom_pmic_gpio: add support for pm8550-gpio
Add support for PM8550 GPIO controller variant, keep read-only
until the GPIO and Pinctrl setup is fixed for new PMICs.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Wed, 10 Apr 2024 17:52:39 +0000 (19:52 +0200)]
qcom_defconfig: enable pinctrl for new qcm2290/sm6115/sm8250
Enable the clock and pinctrl drivers for qcm2290, sm6115, and sm8250.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Wed, 10 Apr 2024 17:52:38 +0000 (19:52 +0200)]
pinctrl: qcom: add sm8250 pinctrl driver
This SoC features a pinctrl block with north, south, and west tiles
accessible to the AP.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Wed, 10 Apr 2024 17:52:37 +0000 (19:52 +0200)]
pinctrl: qcom: add sm6115 pinctrl driver
This SoC features a pinctrl block with west, east, and south tiles.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Caleb Connolly [Wed, 10 Apr 2024 17:52:36 +0000 (19:52 +0200)]
pinctrl: qcom: add qcm2290 pinctrl driver
This SoC has a basic pinctrl block with no tiles.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:15:12 +0000 (10:15 +0200)]
qcom_defconfig: enable SM8550 & SM8650 pinctrl driver
Enable the SM8550 & SM8650 pinctrl drivers for Qualcomm defconfig.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:15:11 +0000 (10:15 +0200)]
pinctrl: qcom: Add SM8650 pinctrl driver
Add pinctrl driver for the TLMM block found in the SM8650 SoC.
This driver only handles the gpio and qup2_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Fri, 5 Apr 2024 08:15:10 +0000 (10:15 +0200)]
pinctrl: qcom: Add SM8550 pinctrl driver
Add pinctrl driver for the TLMM block found in the SM8550 SoC.
This driver only handles the gpio and qup1_se7 pinmux, and makes sure
the pinconf applies on SDC2 pins.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 10 Apr 2024 16:01:13 +0000 (18:01 +0200)]
qcom_defconfig: enable the Qualcomm Synopsys eUSB2 PHY driver
Enable the Qualcomm Synopsys eUSB2 PHY driver in Qualcomm defconfig.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Neil Armstrong [Wed, 10 Apr 2024 16:01:12 +0000 (18:01 +0200)]
phy: qcom: add Synopsys eUSB2 PHY driver
Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
Tom Rini [Mon, 22 Apr 2024 21:10:21 +0000 (15:10 -0600)]
Prepare v2024.07-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 22 Apr 2024 17:02:16 +0000 (11:02 -0600)]
Merge patch series "configs: apple: Switch to standard boot + small adjustments"
Janne Grunau <j@jannau.net> says:
This series contains a few misc config changes for Apple silicon
systems:
- switch from the deprecated distro boot scripts to standard boot
- allows EFI console resizing based on the video console size
- enables 16x32 bitmap fonts as Apple devices come with high DPI
displays
- enables 64-bit LBA addressing
Janne Grunau [Thu, 18 Apr 2024 19:00:29 +0000 (21:00 +0200)]
arm: apple: Do not list bootflows on boot
The bootflow list is only seen briefly and is probably more confusing
than helpful.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Janne Grunau [Thu, 18 Apr 2024 19:00:28 +0000 (21:00 +0200)]
arm: apple: Switch to standard boot
Use standard boot instead of the distro boot scripts. Use
BOOTSTD_FULL instead of BOOTSTD_DEFAULTS for easier interactive use.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Janne Grunau [Thu, 18 Apr 2024 19:00:27 +0000 (21:00 +0200)]
configs: apple: Enable CMD_SELECT_FONT and FONT_16X32
Apple devices have high DPI displays so the larger fonts are preferable
for improved readability. This does not yet change the used font based
on the display's pixel density so the standard 8x16 font is still used
by default.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Janne Grunau <j@jannau.net>
Janne Grunau [Thu, 18 Apr 2024 19:00:26 +0000 (21:00 +0200)]
configs: apple: Use "vidconsole,serial" as stdout/stderr
The display size querying in efi_console relies on this order. The
display should be the primary output device and should be used to
display more than 80x25 chars.
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Janne Grunau <j@jannau.net>
Hector Martin [Thu, 18 Apr 2024 19:00:25 +0000 (21:00 +0200)]
apple_m1_defconfig: Turn on CONFIG_SYS_64BIT_LBA
This makes USB HDDs >2TiB work. The only reason this hasn't bitten us
for the internal NVMe yet is the 4K sector size, because the largest SSD
Apple sells is 8TB and we can handle up to 16TiB with that sector size.
Close call.
Signed-off-by: Hector Martin <marcan@marcan.st>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Neal Gompa <neal@gompa.dev>
Signed-off-by: Janne Grunau <j@jannau.net>
Tom Rini [Mon, 22 Apr 2024 17:01:56 +0000 (11:01 -0600)]
Merge patch series "Kconfig: some cleanups"
Michal Simek <michal.simek@amd.com> says:
I looked as cleaning up some dependencies and I found that qconfig is
reporting some issues. This series is fixing some of them. But there are
still some other pending. That's why please go and fix them if they are
related to your board.
UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in
a loop you will find some other issue with copyright chars or some issues
in files taken from the Linux kernel like DTs. They should be likely fixed
in the kernel first.
Based on discussion I am ignoring names too.
Michal Simek [Tue, 16 Apr 2024 06:55:19 +0000 (08:55 +0200)]
common: Convert *.c/h from UTF-8 to ASCII enconfing
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or
names are converted.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Behún <kabel@kernel.org>
Michal Simek [Tue, 16 Apr 2024 06:55:18 +0000 (08:55 +0200)]
Kconfig: Make all Kconfig encoding ascii
Some of Kconfigs are using utf-8 encoding because of used chars. Convert
all of them to ascii enconging. Based on discussion ASCII should be used in
general with the exception of names.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Michal Simek [Tue, 16 Apr 2024 06:55:17 +0000 (08:55 +0200)]
Kconfig: Add missing quotes around default string value
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
warning: style: quotes recommended around default value for string symbol
EFI_VAR_SEED_FILE (defined at lib/efi_loader/Kconfig:130)
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Michal Simek [Tue, 16 Apr 2024 06:55:16 +0000 (08:55 +0200)]
Kconfig: Add missing quotes around source file
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
drivers/crypto/Kconfig:9: warning: style: quotes recommended around
'drivers/crypto/nuvoton/Kconfig' in 'source drivers/crypto/nuvoton/Kconfig'
Signed-off-by: Michal Simek <michal.simek@amd.com>
Michal Simek [Tue, 16 Apr 2024 06:55:15 +0000 (08:55 +0200)]
Kconfig: Remove trailing whitespace in its prompt
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever.
Error look like this:
warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or
trailing whitespace in its prompt
Signed-off-by: Michal Simek <michal.simek@amd.com>
Tom Rini [Mon, 22 Apr 2024 16:44:54 +0000 (10:44 -0600)]
doc: release_cycle: Note when next branch opens
While I have said this in various release emails, it should be
documented here as well that the next branch opens with the second
release candidate.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 22 Apr 2024 16:24:34 +0000 (10:24 -0600)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
Not many and nothing really exciting this time: there are more patches
in fly, but they are not ready yet. I will also send some DT updates
and new board defconfig files later, once they have seen the list. I am
aware of the USB rebasing repo efforts, but would like to see how this
plays out, also we have one compatibility issue that I painstakingly
work around in the U-Boot tree for the last three years or so. So for
now I stick to the previous approach.
So now just some easy changes: support for USB peripheral mode on the
Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup
patches.
The branch passed the gitlab CI run, and brief boot testing on some
boards didn't turn up any issues.
Tom Rini [Mon, 22 Apr 2024 14:29:10 +0000 (08:29 -0600)]
Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Svyatoslav Ryhel [Sun, 7 Jan 2024 09:17:47 +0000 (11:17 +0200)]
board: tegra30: switch to button cmd
Use recently added ability to assign commands to buttons via env.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Wed, 31 Jan 2024 08:08:06 +0000 (10:08 +0200)]
ARM: tegra: transformer-t30: bind Hall sensor
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Wed, 31 Jan 2024 08:07:51 +0000 (10:07 +0200)]
ARM: tegra: grouper: bind Hall sensor
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Tue, 25 Apr 2023 15:21:32 +0000 (18:21 +0300)]
board: asus: tf700t: bind tc358768 bridge and panel
Of all T30 transformers, only the TF700T has a FullHD DSI panel,
which is connected via tc358768 RGB to DSI bridge. Since the
bridge driver is available now, TF700T can have video support.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Thu, 25 Jan 2024 12:24:22 +0000 (14:24 +0200)]
board: asus: transformer-t30: enable I2C_MUX only for TF700T
Of all T30 transformers, only the TF700T uses GPIO i2c muxing
for one of the i2c lines and needs this driver to properly work.
Disable this configuration for all transformers except tf700t
in their fragments.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Thu, 25 Jan 2024 12:19:06 +0000 (14:19 +0200)]
board: asus: tf600t: enable TEGRA20_SLINK only for TF600T
Of all T30 transformers, only the TF600T uses SPI flash and
needs SLINK driver to work with it. Move this configuration
to the tf600t fragment from common defconfig.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Jonas Schwöbel [Sun, 21 Jan 2024 16:18:03 +0000 (18:18 +0200)]
ARM: tegra: Enable UART-E for T20 and T30
T20 and T30 have 5 UARTs, while T114+ have only 4. Fix this by
adding missing UARTE Kconfig for T20/T30.
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Sat, 20 Jan 2024 13:06:23 +0000 (15:06 +0200)]
board: asus: transformer-t30: set the correct pinmux lock and io-reset
For lock and io-reset pins 0 is the default value, while 1 is disabled
and 2 is enabled. This should be corrected to avoid regressions.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Fri, 19 Jan 2024 11:28:54 +0000 (13:28 +0200)]
board: asus: tf600t: adjust LV pinmux
TF600T is pretty picky in terms of LV pinmux configuration.
The wrong setup will cause issues with eMMC and video.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Wed, 17 Jan 2024 16:32:21 +0000 (18:32 +0200)]
board: asus: tf600t: configure SPI pinmux
Unlike all other transformers, TF600T has an SPI flash to store
boot firmware and requires precise SPI pinmux configuration.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Jonas Schwöbel [Fri, 19 Jan 2024 13:04:46 +0000 (15:04 +0200)]
board: asus: lg_x3: endeavoru: remove CONFIG_SYS_L2CACHE_OFF
CONFIG_SYS_L2CACHE_OFF is not affecting these devices in any way.
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Sun, 14 Jan 2024 19:39:33 +0000 (21:39 +0200)]
board: tegra30: switch to standard boot
Switch transformer, endeavoru, grouper and x3_t30 boards
to bootflow scan.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Sat, 6 Jan 2024 20:33:59 +0000 (22:33 +0200)]
ARM: tegra: move to standard boot
Drop the distro-boot scripts and use standard boot instead.
Inspired by:
'commit
7755dc58af7b ("rockchip: Move to standard boot")'
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Svyatoslav Ryhel [Sun, 7 Jan 2024 14:31:43 +0000 (16:31 +0200)]
ARM: dts: paz00: remove display-timings node
Paz00 can have multiple panels with different timings, but they
all share common feature - panel exposes EDID.
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Andre Przywara [Thu, 7 Dec 2023 15:43:21 +0000 (15:43 +0000)]
sunxi: sun9i: make more clock functions SPL only
In clock_sun9i.c, responsible for (mostly early) clock setup on the
Allwinner A80 SoC, many functions are only needed by the SPL, and are
thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM, and
they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Move some functions around, to group all SPL-only function within
one #ifdef guard. Some functions were exported, but never used outside
of this file, so remove their prototypes from the header file and mark
them as static.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 15:42:47 +0000 (15:42 +0000)]
sunxi: sun8i_a83t: make more clock functions SPL only
In clock_sun8i_a83t.c, responsible for (mostly early) clock setup on the
Allwinner A83T SoC, many functions are only needed by the SPL, and are
thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 16:07:05 +0000 (16:07 +0000)]
sunxi: sun50i_h6: make more clock functions SPL only
In clock_sun50i_h6.c, responsible for (mostly early) clock setup on
newer generation Allwinner SoCs, many functions are only needed by the
SPL, and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only. By moving the clock_get_pll6()
function to the end of the file, all SPL-only clocks can be contained
within one #ifdef guard.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 16:06:51 +0000 (16:06 +0000)]
sunxi: sun6i: make more clock functions SPL only
In clock_sun6i.c, responsible for (mostly early) clock setup on older
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 16:06:51 +0000 (16:06 +0000)]
sunxi: sun4i: make more clock functions SPL only
In clock_sun4i.c, responsible for (mostly early) clock setup on early
generation Allwinner SoCs, many functions are only needed by the SPL,
and are thus already guarded by CONFIG_SPL_BUILD.
Over the years drivers like for the UART or I2C were converted to DM,
so they care about clock setup themselves now, by using a proper DM clock
driver.
This means those devices need the clock setup functions here for the SPL
only. Include those functions into the existing CONFIG_SPL_BUILD guards,
so they are compiled for the SPL only.
This avoids unnecessary code in U-Boot proper and helps further
refactoring. Add some comments on the way to help understanding of the
file.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 16:06:04 +0000 (16:06 +0000)]
sunxi: compile clock.c for SPL only
With the clock_twi_onoff() function now being called only from the SPL,
the whole clock.c file in arch/arm/mach-sunxi is needed by SPL code
only.
Remove the redundant #ifdef from the clock_init() function, actually
this function was already only called from the SPL.
Then adjust the Makefile to compile clock.c only with CONFIG_SPL_BUILD
defined.
This avoids unnecessary code in U-Boot proper and allows further
refactoring and code-split between the SPL and U-Boot proper.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 2 Jan 2024 15:02:51 +0000 (15:02 +0000)]
sunxi: remove unneeded i2c_init_board() call for U-Boot proper
The driver used for the Allwinner I2C IP is using proper DT and DM
enablement for a while: we enable the clock gate and de-assert the reset
line in the driver's probe() routine, and the pinmux setup is taken care
of by the DM framework.
This means the explicit call to the i2c_init_board() routine is not
needed for U-Boot proper. As the board_init() function in board.c is
only called for U-Boot proper, we can remove the call, something that
the comment there hinted at already.
Fix the comment for the board_init() function on the way: we were not
really doing board specific setup there. The fact that this function
is called from U-Boot proper only is probably more helpful for reasoning
about this code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 7 Dec 2023 15:09:51 +0000 (15:09 +0000)]
sunxi: move #ifdef guards around tzpc_init() to header file
Some later 32-bit SoCs require some setup of the Secure Peripherals
Controller, which is handled in tzpc_init().
At the moment this is guarded in board.c by some #ifdefs selecting the
SoCs that need it.
Move those #ifdef guards into the header file, providing an empty stub
function for all other SoCs, so that the #ifdefs can be removed from the
.c file, to improve readability.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>