From: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Date: Mon, 19 Dec 2022 11:31:26 +0000 (+0100)
Subject: clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
X-Git-Tag: v2025.01-rc5-pxa1908~1107^2~3
X-Git-Url: http://git.dujemihanovic.xyz/html/static/%7B%7B%20%28.OutputFormats.Get?a=commitdiff_plain;h=4a18d2303927a22f356c9be102a2c8b4a3df43fa;p=u-boot.git

clk: imx8mn: fix imx8mn_enet_phy_sels clocks list

[backport from linux commit 2626cf67f20b28446dfc3a5b9493dd535cdb747b]

According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):

     Clock Root         offset     Source Select (CCM_TARGET_ROOTn[MUX])
        ...              ...                    ...
 ENET_PHY_REF_CLK_ROOT  0xAA80            000 - 24M_REF_CLK
                                          001 - SYSTEM_PLL2_DIV20
                                          010 - SYSTEM_PLL2_DIV8
                                          011 - SYSTEM_PLL2_DIV5
                                          100 - SYSTEM_PLL2_DIV2
                                          101 - AUDIO_PLL1_CLK
                                          110 - VIDEO_PLL_CLK
                                          111 - AUDIO_PLL2_CLK
        ...              ...                    ...

while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
---

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index a2c7c63ef7..692823e74b 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -41,7 +41,7 @@ static const char *imx8mn_enet_timer_sels[] = {"clock-osc-24m", "sys_pll2_100m",
 					       "clk_ext3", "clk_ext4", "video_pll_out", };
 
 static const char *imx8mn_enet_phy_sels[] = {"clock-osc-24m", "sys_pll2_50m", "sys_pll2_125m", "sys_pll2_200m",
-					     "sys_pll2_500m", "video_pll_out", "audio_pll2_out", };
+					     "sys_pll2_500m", "audio_pll1_out", "video_pll_out", "audio_pll2_out", };
 #endif
 
 static const char *imx8mn_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",