From 24c969785b637338e87969e527f11d2ea346e5dc Mon Sep 17 00:00:00 2001 From: =?utf8?q?Duje=20Mihanovi=C4=87?= Date: Wed, 1 Jan 2025 13:50:15 +0100 Subject: [PATCH] sync up with mailing list patchset --- arch/arm/dts/pxa1908.dtsi | 14 +++++++------- configs/coreprimevelte_defconfig | 4 +--- drivers/serial/ns16550.c | 1 + include/configs/pxa1908.h | 6 ++++++ 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi index 41ffe0ea89..e8ec2606c2 100644 --- a/arch/arm/dts/pxa1908.dtsi +++ b/arch/arm/dts/pxa1908.dtsi @@ -16,28 +16,28 @@ cpu0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 0>; enable-method = "psci"; }; cpu1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 1>; enable-method = "psci"; }; cpu2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 2>; enable-method = "psci"; }; cpu3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0 3>; enable-method = "psci"; }; @@ -82,21 +82,21 @@ ranges = <0 0 0xd4000000 0x200000>; uart0: serial@17000 { - compatible = "ns16550"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0x17000 0x1000>; clock-frequency = <14745600>; reg-shift = <2>; }; uart1: serial@18000 { - compatible = "ns16550"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0x18000 0x1000>; clock-frequency = <14745600>; reg-shift = <2>; }; uart2: serial@36000 { - compatible = "ns16550"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0x36000 0x1000>; clock-frequency = <117000000>; reg-shift = <2>; diff --git a/configs/coreprimevelte_defconfig b/configs/coreprimevelte_defconfig index 3815bb09fe..0511666920 100644 --- a/configs/coreprimevelte_defconfig +++ b/configs/coreprimevelte_defconfig @@ -10,11 +10,9 @@ CONFIG_TARGET_COREPRIMEVELTE=y CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_ARMV8_PSCI=y CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y -CONFIG_CMD_CPU=y CONFIG_CMD_DM=y CONFIG_OF_BOARD=y -CONFIG_CPU=y -CONFIG_CPU_ARMV8=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 3f6860f391..eab1933950 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -614,6 +614,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 }, { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 }, { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, + { .compatible = "intel,xscale-uart", .data = PORT_NS16550 }, {} }; #endif /* OF_REAL */ diff --git a/include/configs/pxa1908.h b/include/configs/pxa1908.h index 1071c32bfa..b0d6cdfeb7 100644 --- a/include/configs/pxa1908.h +++ b/include/configs/pxa1908.h @@ -3,6 +3,10 @@ * Copyright (c) 2024 * Duje Mihanović */ + +#ifndef __PXA1908_H +#define __PXA1908_H + #define CFG_SYS_SDRAM_BASE 0x1000000 #define CFG_SYS_INIT_RAM_ADDR 0x10000000 #define CFG_SYS_INIT_RAM_SIZE 0x4000 @@ -10,3 +14,5 @@ #define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 } #define CFG_EXTRA_ENV_SETTINGS \ "bootcmd=bootm $prevbl_initrd_start_addr\0" + +#endif -- 2.39.5