From aef59e5cc450f403478f799bbb0f0647ff28a3c3 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 12 Dec 2018 06:12:38 -0800 Subject: [PATCH] riscv: Update supports_extension() to use desc from cpu driver This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel --- arch/riscv/cpu/cpu.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d3c59da34b..fc7c9b3751 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -5,8 +5,10 @@ #include #include +#include #include #include +#include /* * prior_stage_fdt_address must be stored in the data section since it is used @@ -16,7 +18,31 @@ phys_addr_t prior_stage_fdt_address __attribute__((section(".data"))); static inline bool supports_extension(char ext) { +#ifdef CONFIG_CPU + struct udevice *dev; + char desc[32]; + + uclass_find_first_device(UCLASS_CPU, &dev); + if (!dev) { + debug("unable to find the RISC-V cpu device\n"); + return false; + } + if (!cpu_get_desc(dev, desc, sizeof(desc))) { + /* skip the first 4 characters (rv32|rv64) */ + if (strchr(desc + 4, ext)) + return true; + } + + return false; +#else /* !CONFIG_CPU */ +#ifdef CONFIG_RISCV_MMODE return csr_read(misa) & (1 << (ext - 'a')); +#else /* !CONFIG_RISCV_MMODE */ +#warning "There is no way to determine the available extensions in S-mode." +#warning "Please convert your board to use the RISC-V CPU driver." + return false; +#endif /* CONFIG_RISCV_MMODE */ +#endif /* CONFIG_CPU */ } static int riscv_cpu_probe(void) -- 2.39.5