From a95800e881a8df837f0c4121a2cd560a4c02bd2f Mon Sep 17 00:00:00 2001
From: Paul Burton <paul.burton@imgtec.com>
Date: Thu, 9 Jun 2016 13:09:51 +0100
Subject: [PATCH] MIPS: Fix invalidate_dcache_range to operate on L1 Dcache
Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
---
arch/mips/lib/cache.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 5f520c069f..db81953f86 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
if (start_addr == stop)
return;
- cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
+ cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}
--
2.39.5