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4 years agoarm64: dts: a3720: add support for espressobin with populated emmc
Andre Heider [Fri, 4 Sep 2020 15:33:54 +0000 (17:33 +0200)]
arm64: dts: a3720: add support for espressobin with populated emmc

Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.

Signed-off-by: Andre Heider <a.heider@gmail.com>
4 years agoarm64: dts: armada-3720-espressobin: split common parts to .dtsi
Andre Heider [Fri, 4 Sep 2020 15:33:53 +0000 (17:33 +0200)]
arm64: dts: armada-3720-espressobin: split common parts to .dtsi

Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.

The dts itself is imported from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
4 years agoarm64: dts: armada-3720-espressobin: use Linux model/compatible strings
Andre Heider [Fri, 2 Oct 2020 05:51:12 +0000 (07:51 +0200)]
arm64: dts: armada-3720-espressobin: use Linux model/compatible strings

Fix the actual board vendor and ease synching dts files from Linux.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agospi: mvebu_a3700_spi: add support for cs-gpios
George Hilliard [Wed, 30 Sep 2020 14:28:21 +0000 (09:28 -0500)]
spi: mvebu_a3700_spi: add support for cs-gpios

The device tree has a way to specify GPIO lines as chip selects.  From
the binding docs:

    So if for example the controller has 2 CS lines, and the cs-gpios
    property looks like this:

    cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;

    Then it should be configured so that num_chipselect = 4 with the
    following mapping:

    cs0 : &gpio1 0 0
    cs1 : native
    cs2 : &gpio1 1 0
    cs3 : &gpio1 2 0

Add support for this, while retaining backward-compatibility with
existing device trees; the driver will preserve existing behavior if a
cs-gpios list is not given, or if a particular line is specified as <0>
(native).

This implementation is inspired by similar implementations in
neighboring drivers for other platforms: atmega, mxc, etc.

Signed-off-by: George Hilliard <ghilliar@amazon.com>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agoarm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking
Luka Kovacic [Fri, 28 Aug 2020 22:35:51 +0000 (00:35 +0200)]
arm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking

Add support for the marvell,armada8040-puzzle-m801 compatible string
in the board/Marvell/mvebu_armada-8k/board.c file to initialize the
networking on iEi Puzzle-M801 board (2x CP1 1 Gb ports).

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agoarm: mvebu: Initial iEi Puzzle-M801 support
Luka Kovacic [Fri, 28 Aug 2020 22:35:50 +0000 (00:35 +0200)]
arm: mvebu: Initial iEi Puzzle-M801 support

Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.

Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agonet: Add NIC controller driver for OcteonTX2
Suneel Garapati [Wed, 26 Aug 2020 12:37:42 +0000 (14:37 +0200)]
net: Add NIC controller driver for OcteonTX2

Adds support for Network Interface controllers found on
OcteonTX2 SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agonet: Add NIC controller driver for OcteonTX
Suneel Garapati [Wed, 26 Aug 2020 12:37:33 +0000 (14:37 +0200)]
net: Add NIC controller driver for OcteonTX

Adds support for Network Interface controllers found on
OcteonTX SoC platforms.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
4 years agomtd: nand: Add NAND controller driver for OcteonTX
Suneel Garapati [Wed, 26 Aug 2020 12:37:22 +0000 (14:37 +0200)]
mtd: nand: Add NAND controller driver for OcteonTX

Adds support for NAND controllers found on OcteonTX or
OcteonTX2 SoC platforms. Also includes driver to support
Hardware ECC using BCH HW engine found on these platforms.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
4 years agoMerge branch '2020-10-12-assorted-encryption-changes'
Tom Rini [Tue, 13 Oct 2020 14:04:17 +0000 (10:04 -0400)]
Merge branch '2020-10-12-assorted-encryption-changes'

- Fix verified boot on BE targets
- Add support for multiple required keys in verified boots
- Add support for Initialization Vectors in AES keys in FIT images
- Assorted fixes in the RSA code

4 years agolib: rsa: superfluous initialization in rsa_verify()
Heinrich Schuchardt [Thu, 8 Oct 2020 18:53:13 +0000 (20:53 +0200)]
lib: rsa: superfluous initialization in rsa_verify()

Remove initialization of ret with unused value.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agorsa: fix retrieving public exponent on big-endian systems
Rasmus Villemoes [Tue, 6 Oct 2020 10:09:45 +0000 (12:09 +0200)]
rsa: fix retrieving public exponent on big-endian systems

Commit fdf0819afb (rsa: fix alignment issue when getting public
exponent) changed the logic to avoid doing an 8-byte access to a
possibly-not-8-byte-aligned address.

However, using rsa_convert_big_endian is wrong: That function converts
an array of big-endian (32-bit) words with the most significant word
first (aka a BE byte array) to an array of cpu-endian words with the
least significant word first. While the exponent is indeed _stored_ as
a big-endian 64-bit word (two BE words with MSW first), we want to
extract it as a cpu-endian 64 bit word. On a little-endian host,
swapping the words and byte-swapping each 32-bit word works, because
that's the same as byte-swapping the whole 64 bit word. But on a
big-endian host, the fdt32_to_cpu are no-ops, but
rsa_convert_big_endian() still does the word-swapping, breaking
verified boot.

To fix that, while still ensuring we don't do unaligned accesses, add
a little helper that first memcpy's the bytes to a local fdt64_t, then
applies fdt64_to_cpu(). [The name is chosen based on the
[bl]eXX_to_cpup in linux/byteorder/generic.h].

Fixes: fdf0819afb ("rsa: fix alignment issue when getting public exponent")
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agolib: rsa: check algo match in rsa_verify_with_keynode
Matthieu CASTET [Wed, 23 Sep 2020 17:11:44 +0000 (19:11 +0200)]
lib: rsa: check algo match in rsa_verify_with_keynode

The algo name should match between the FIT's signature node and the
U-Boot's control FDT.

If we do not check it, U-Boot's control FDT can expect sha512 hash but
nothing will prevent to accept image with sha1 hash if the signature is correct.

Signed-off-by: Matthieu CASTET <castet.matthieu@free.fr>
4 years agofit: cipher: aes: allow to read the IV in the FIT image
Philippe Reynes [Thu, 17 Sep 2020 13:01:47 +0000 (15:01 +0200)]
fit: cipher: aes: allow to read the IV in the FIT image

This commit add the support in u-boot to read the IV
in the FIT image instead of u-boot device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
4 years agofit: cipher: aes: allow to store the IV in the FIT image
Philippe Reynes [Thu, 17 Sep 2020 13:01:46 +0000 (15:01 +0200)]
fit: cipher: aes: allow to store the IV in the FIT image

Binaries may be encrypted in a FIT image with AES. This
algo needs a key and an IV (Initialization Vector). The
IV is provided in a file (pointer by iv-name-hint in the
ITS file) when building the ITB file.

This commits adds provide an alternative way to manage
the IV. If the property iv-name-hint is not provided in
the ITS file, the tool mkimage will generate an random
IV and store it in the FIT image.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
4 years agolib/hashtable: remove superfluous check
Heinrich Schuchardt [Thu, 20 Aug 2020 17:57:45 +0000 (19:57 +0200)]
lib/hashtable: remove superfluous check

We assign first_deleted = 0. There is no need to check its value without
any further assignment in between.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agodoc: verified-boot: add required-mode information
Thirupathaiah Annapureddy [Mon, 17 Aug 2020 06:01:11 +0000 (23:01 -0700)]
doc: verified-boot: add required-mode information

Add documentation about 'required-mode' property in /signature node
in U-Boot's control FDT.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agotest: vboot: add tests for multiple required keys
Thirupathaiah Annapureddy [Mon, 17 Aug 2020 06:01:10 +0000 (23:01 -0700)]
test: vboot: add tests for multiple required keys

This patch adds vboot tests to verify the support for multiple
required keys using new required-mode DTB policy.

This patch also fixes existing test where dev
key is assumed to be marked as not required, although
it is marked as required.

Note that this patch re-added sign_fit_norequire().
sign_fit_norequire() was removed as part of the following:
commit b008677daf2a ("test: vboot: Fix pylint errors").
This patch leverages sign_fit_norequire() to fix the
existing bug.

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agovboot: add DTB policy for supporting multiple required conf keys
Thirupathaiah Annapureddy [Mon, 17 Aug 2020 06:01:09 +0000 (23:01 -0700)]
vboot: add DTB policy for supporting multiple required conf keys

Currently FIT image must be signed by all required conf keys. This means
Verified Boot fails if there is a signature verification failure
using any required key in U-Boot DTB.

This patch introduces a new policy in DTB that can be set to any required
conf key. This means if verified boot passes with one of the required
keys, U-Boot will continue the OS hand off.

There were prior attempts to address this:
https://lists.denx.de/pipermail/u-boot/2019-April/366047.html
The above patch was failing "make tests".
https://lists.denx.de/pipermail/u-boot/2020-January/396629.html

Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agoMerge branch 'for-next' of https://github.com/lftan/u-boot
Tom Rini [Mon, 12 Oct 2020 11:55:17 +0000 (07:55 -0400)]
Merge branch 'for-next' of https://github.com/lftan/u-boot

4 years agoMerge tag 'ti-v2021.01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
Tom Rini [Mon, 12 Oct 2020 11:26:57 +0000 (07:26 -0400)]
Merge tag 'ti-v2021.01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

- Minor cleanup on K3 env variables
- Fix OSPI compatible for J721e
- Drop unused property in omap-usb2-phy
- Update Maintainer for am335x-guardian board.

4 years agophy: omap-usb2-phy: Drop usage of "ti, dis-chg-det-quirk" DT property
Vignesh Raghavendra [Thu, 8 Oct 2020 09:28:38 +0000 (14:58 +0530)]
phy: omap-usb2-phy: Drop usage of "ti, dis-chg-det-quirk" DT property

"ti,dis-chg-det-quirk" property is not part of Linux kernel DT binding
documentation.  Therefore drop this and instead use soc_device_match()
to distinguish b/w AM654 SR1.0 and SR2.0 devices similar to Linux kernel
driver.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
4 years agoconfigs: am65x_evm: Use DEFAULT_LINUX_BOOT_ENV and remove overlayaddr
Nishanth Menon [Thu, 8 Oct 2020 02:48:01 +0000 (21:48 -0500)]
configs: am65x_evm: Use DEFAULT_LINUX_BOOT_ENV and remove overlayaddr

Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest
of TI platforms as defined in ti_armv7_common.h

This avoids the standard pitfalls we've had with kernel images and fdt
addresses stomping on each other.

As part of this process, redefine overlayaddr to be dtboaddr (defined
in ti_armv7_common.h for this very purpose) and get rid of the
definition of overlayaddr..

Signed-off-by: Nishanth Menon <nm@ti.com>
4 years agoconfigs: j721e_evm: Get rid of overlayaddr
Nishanth Menon [Thu, 8 Oct 2020 02:48:00 +0000 (21:48 -0500)]
configs: j721e_evm: Get rid of overlayaddr

Now that we dont have any further users of overlayaddr, get rid of it.

Signed-off-by: Nishanth Menon <nm@ti.com>
4 years agoenv: ti: ufs: Use dtboaddr instead of overlayaddr
Nishanth Menon [Thu, 8 Oct 2020 02:47:59 +0000 (21:47 -0500)]
env: ti: ufs: Use dtboaddr instead of overlayaddr

Use dtboaddr to define the overlay address common to all TI platforms
instead of creating a new overlayaddr for the purpose.

Signed-off-by: Nishanth Menon <nm@ti.com>
4 years agoconfigs: j721e_evm: Use DEFAULT_LINUX_BOOT_ENV
Nishanth Menon [Thu, 8 Oct 2020 02:47:58 +0000 (21:47 -0500)]
configs: j721e_evm: Use DEFAULT_LINUX_BOOT_ENV

Use DEFAULT_LINUX_BOOT_ENV to define the standard addresses used in rest
of TI platforms as defined in ti_armv7_common.h

This avoids the standard pitfalls we've had with kernel images and fdt
addresses stomping on each other.

As part of this process, redefine overlayaddr to be dtboaddr (defined
in ti_armv7_common.h for this very purpose).. we will get rid of
overlayaddr later in the series.

Signed-off-by: Nishanth Menon <nm@ti.com>
4 years agodma: ti: k3-udma: Reset the channel during release
Vignesh Raghavendra [Thu, 17 Sep 2020 14:41:22 +0000 (20:11 +0530)]
dma: ti: k3-udma: Reset the channel during release

Reset the channel completely during channel release in order to clear
teardown bit before handing over to next user or jumping to Linux.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
4 years agoconfigs: am335x_evm_defconfig: Enable CONFIG_OF_LIBFDT_OVERLAY
Vignesh Raghavendra [Wed, 16 Sep 2020 10:53:20 +0000 (16:23 +0530)]
configs: am335x_evm_defconfig: Enable CONFIG_OF_LIBFDT_OVERLAY

This enables applying DTBOs at U-Boot prompt before booting to kernel.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
4 years agoboard: ti: j721e: Fix OSPI node compatible
Vignesh Raghavendra [Thu, 17 Sep 2020 11:18:16 +0000 (16:48 +0530)]
board: ti: j721e: Fix OSPI node compatible

Update detect_enable_hyperflash() to look for "ti,am654-ospi" compatible
to match the upstream DT node.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
4 years agoam335x, guardian: update the maintainer list
Moses Christopher [Mon, 7 Sep 2020 09:44:47 +0000 (09:44 +0000)]
am335x, guardian: update the maintainer list

I am leaving Bosch, so replacing myself with Gireesh

Signed-off-by: Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
4 years agoMerge branch '2020-10-10-log-improvements'
Tom Rini [Sun, 11 Oct 2020 19:22:05 +0000 (15:22 -0400)]
Merge branch '2020-10-10-log-improvements'

- Assorted improvements to our log functionality.

4 years agodoc: remove redundant doc/README.log
Heinrich Schuchardt [Mon, 14 Sep 2020 08:12:19 +0000 (10:12 +0200)]
doc: remove redundant doc/README.log

doc/README.log was already moved to doc/develop/logging.rst but has been
recreated by an incorrect merge.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agolog: syslog: Handle errors in net_init
Sean Anderson [Sat, 12 Sep 2020 21:45:44 +0000 (17:45 -0400)]
log: syslog: Handle errors in net_init

Since the previous patch, net_init now exposes some errors, so check for
them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agonet: Expose some errors generated in net_init
Sean Anderson [Sat, 12 Sep 2020 21:45:43 +0000 (17:45 -0400)]
net: Expose some errors generated in net_init

net_init does not always succeed, and there is no existing mechanism to
discover errors. This patch allows callers of net_init (such as net_init)
to handle errors. The root issue is that eth_get_dev can fail, but
net_init_loop doesn't expose that. The ideal way to fix eth_get_dev would
be to return an error with ERR_PTR, but there are a lot of callers, and all
of them just check if it's NULL. Another approach would be to change the
signature to something like

int eth_get_dev(struct udevice **pdev)

but that would require rewriting all of the many callers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
4 years agolog: Disable the syslog driver by default
Simon Glass [Sat, 12 Sep 2020 18:28:50 +0000 (12:28 -0600)]
log: Disable the syslog driver by default

This driver interferes with other sandbox tests since it causes log output
to be interspersed with "No ethernet found." messages. Disable this driver
by default.

Enable it for the syslog tests so that they still pass.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agolog: Add a way to enable/disable a log device
Simon Glass [Sat, 12 Sep 2020 18:28:49 +0000 (12:28 -0600)]
log: Add a way to enable/disable a log device

At present all log devices are enabled by default. Add a function to allow
devices to be disabled or enabled at runtime.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agolog: Drop #ifdef in log_test
Simon Glass [Sat, 12 Sep 2020 18:28:48 +0000 (12:28 -0600)]
log: Drop #ifdef in log_test

This is not needed as the Makefile only builds the file if CONFIG_LOG_TEST
is enabled. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agolog: Add a flag to enable log drivers
Simon Glass [Sat, 12 Sep 2020 18:28:47 +0000 (12:28 -0600)]
log: Add a flag to enable log drivers

At present there is no way to disable a log driver. But the syslog driver
causes (attempted) network traffic in sandbox every time a log message
is printed, which is often.

Add a flag to enable a log driver. Adjust struct log_device to use a short
for next_filter_num so that no more memory is used for devices. Also fix
a missing line in the struct log_driver comment while here.

To maintain compatibility, enable it for all drivers for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agolib: Allow hexdump to be used in SPL
Simon Glass [Sat, 12 Sep 2020 17:13:35 +0000 (11:13 -0600)]
lib: Allow hexdump to be used in SPL

It is sometimes useful to output hex dumps in SPL. Add a config option to
allow this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
4 years agolog: Allow LOG_DEBUG to always enable log output
Simon Glass [Sat, 12 Sep 2020 17:13:34 +0000 (11:13 -0600)]
log: Allow LOG_DEBUG to always enable log output

At present if CONFIG_LOG enabled, putting LOG_DEBUG at the top of a file
(before log.h inclusion) causes _log() to be executed for every log()
call, regardless of the build- or run-time logging level.

However there is no guarantee that the log record will actually be
displayed. If the current log level is lower than LOGL_DEBUG then it will
not be.

Add a way to signal that the log record should always be displayed and
update log_passes_filters() to handle this.

With the new behaviour, log_debug() will always log if LOG_DEBUG is
enabled.

Move log_test_syslog_nodebug() into its own file since it cannot be made
to work where it is, with LOG_DEBUG defined.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoMerge branch '2020-10-09-kconfig-reorg'
Tom Rini [Fri, 9 Oct 2020 22:10:24 +0000 (18:10 -0400)]
Merge branch '2020-10-09-kconfig-reorg'

- Re-organize a number of Kconfig related entries to be better organized
  for long term maintenance.

4 years agoconfigs: Resync with savedefconfig
Tom Rini [Fri, 9 Oct 2020 16:22:06 +0000 (12:22 -0400)]
configs: Resync with savedefconfig

Rsync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
4 years agoKconfig: Create a new tools menu
Simon Glass [Fri, 11 Sep 2020 02:21:27 +0000 (20:21 -0600)]
Kconfig: Create a new tools menu

At present MKIMAGE_DTC_PATH is in the devicetree menu but not within
'devicetree control' since it does not relate to that. As a result it
shows up in the top menu.

It actually relates to the mkimage tool, so create a new tools menu for it
and move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move BOARD_TYPES under init options
Simon Glass [Fri, 11 Sep 2020 02:21:26 +0000 (20:21 -0600)]
Kconfig: Move BOARD_TYPES under init options

This actually relates to something displayed on start-up, so move it into
that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move BOUNCE_BUFFER under driver options
Simon Glass [Fri, 11 Sep 2020 02:21:25 +0000 (20:21 -0600)]
Kconfig: Move BOUNCE_BUFFER under driver options

This option does not belong at the top level. Move it under generic
driver options.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move VERSION_VARIABLE under environment
Simon Glass [Fri, 11 Sep 2020 02:21:24 +0000 (20:21 -0600)]
Kconfig: Move VERSION_VARIABLE under environment

This relates to the environment so should not be at the top level. Move
it.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: MISC_INIT_R and BOARD_LATE_INIT -> start-up hooks
Simon Glass [Fri, 11 Sep 2020 02:21:23 +0000 (20:21 -0600)]
Kconfig: MISC_INIT_R and BOARD_LATE_INIT -> start-up hooks

These are start-up hooks so put them under that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move startup hooks under init options
Simon Glass [Fri, 11 Sep 2020 02:21:22 +0000 (20:21 -0600)]
Kconfig: Move startup hooks under init options

These hooks relate to U-Boot init so move them under that menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Create a new 'init options' menu
Simon Glass [Fri, 11 Sep 2020 02:21:21 +0000 (20:21 -0600)]
Kconfig: Create a new 'init options' menu

There are quite a few options at the top level relating to U-Boot init.
Move them into their own menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move DEFAULT_FDT_FILE under boot options
Simon Glass [Fri, 11 Sep 2020 02:21:20 +0000 (20:21 -0600)]
Kconfig: Move DEFAULT_FDT_FILE under boot options

This relates to booting since it is the default devicetree provided to
Linux. Move it under the 'boot options' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move SUPPORT_RAW_INITRD under boot options
Simon Glass [Fri, 11 Sep 2020 02:21:19 +0000 (20:21 -0600)]
Kconfig: Move SUPPORT_RAW_INITRD under boot options

This relates to booting, so move it under the 'boot images' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move misc boot options under 'boot options'
Simon Glass [Fri, 11 Sep 2020 02:21:18 +0000 (20:21 -0600)]
Kconfig: Move misc boot options under 'boot options'

There are a number of miscellaneous boot images at the top level of the
kconfig menu. Move these into the 'boot options' menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move CONFIG_BOOTDELAY under autoboot options
Simon Glass [Fri, 11 Sep 2020 02:21:17 +0000 (20:21 -0600)]
Kconfig: Move CONFIG_BOOTDELAY under autoboot options

This option relates to autoboot, so move it there.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move autoboot options under boot options
Simon Glass [Fri, 11 Sep 2020 02:21:16 +0000 (20:21 -0600)]
Kconfig: Move autoboot options under boot options

At present the autoboot options are in cmd/Kconfig but they don't really
relate to commands. They relate to booting, so move this menu under the
boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move boot media under boot options
Simon Glass [Fri, 11 Sep 2020 02:21:15 +0000 (20:21 -0600)]
Kconfig: Move boot media under boot options

This relates to booting, so move it under the boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move boot timing under boot options
Simon Glass [Fri, 11 Sep 2020 02:21:14 +0000 (20:21 -0600)]
Kconfig: Move boot timing under boot options

This relates to booting, so move it under the boot menu.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Move boot menu into common/
Simon Glass [Fri, 11 Sep 2020 02:21:13 +0000 (20:21 -0600)]
Kconfig: Move boot menu into common/

Most of the boot options are in common/Kconfig but that file is already
extremely large. Create a new Kconfig.boot to hold the boot options.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoKconfig: Add a 'Boot options' menu
Simon Glass [Fri, 11 Sep 2020 02:21:12 +0000 (20:21 -0600)]
Kconfig: Add a 'Boot options' menu

There are quite a few boot-related menu options at the top level. Create a
new menu to hold these and move 'Boot images' into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
4 years agoMerge branch '2020-10-08-misc-board-improvements'
Tom Rini [Fri, 9 Oct 2020 12:58:56 +0000 (08:58 -0400)]
Merge branch '2020-10-08-misc-board-improvements'

- Move ASPEED ram driver, update.
- Exhance pinctrl/gpio support, update Kendryte K210 support
- Enhance qemu_arm64 support for a single binary to work with and
  without TF-A

4 years agoMakefile: socfpga: Generate sfp file with 4 SPL images
Chee Hong Ang [Tue, 11 Aug 2020 13:52:30 +0000 (21:52 +0800)]
Makefile: socfpga: Generate sfp file with 4 SPL images

Generate 'u-boot-splx4.sfp' which consist of 4 SPL images required
for booting up Cyclone5/Arria10.

By default, this 'u-boot-splx4.sfp' is generated without extra
padding after each SPL image.

For Cyclone5, 'u-boot-splx4.sfp' contains:
4 x SPL(64KB) = 256KB

For Arria10, 'u-boot-splx4.sfp' contains:
4 x SPL(256KB) = 1024KB

For Cyclone5 using NAND flash image layout for 128 KB memory blocks,
user can 'make' the following target to generate 4 SPL images with
padding:

make u-boot-spl-padx4.sfp

'u-boot-spl-padx4.sfp' contains four 128KB SPL images (each 64KB SPL is
followed by 64KB of zero-padding).
4 x (SPL(64KB) + zero-padding(64KB)) = 512KB

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Remove CONFIG_OF_EMBED
Chee Hong Ang [Thu, 1 Oct 2020 09:15:59 +0000 (02:15 -0700)]
arm: socfpga: soc64: Remove CONFIG_OF_EMBED

CONFIG_OF_EMBED was primarily enabled to support the S10/Agilex
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agotools: socfpgaimage: Add param entry point (ep) support for Arria 10 (v1)
Ley Foon Tan [Tue, 22 Sep 2020 02:19:44 +0000 (10:19 +0800)]
tools: socfpgaimage: Add param entry point (ep) support for Arria 10 (v1)

Add param entry point (ep) support for Arria 10 header. User can pass in
'e' option to mkimage to set the entry point. This is an optional option.

If not specified, default is 0x14.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agotools: socfpgaimage: Add check params function for Arria 10 (v1)
Ley Foon Tan [Wed, 9 Sep 2020 03:34:30 +0000 (11:34 +0800)]
tools: socfpgaimage: Add check params function for Arria 10 (v1)

Add check params function for Arria 10 (header v1).

From [1] page 42, entry point offset should be 4 bytes aligned and
any value smaller than 0x14 is invalid.

Rename existing socfpgaimage_check_params() for v0.

[1]: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_soc_eds.pdf

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: dts: socfpga: arria10: Move to use generic handoff dtsi
Ley Foon Tan [Wed, 8 Jul 2020 08:34:01 +0000 (16:34 +0800)]
arm: dts: socfpga: arria10: Move to use generic handoff dtsi

Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
Dalon Westergreen [Fri, 4 Oct 2019 21:23:48 +0000 (14:23 -0700)]
arm: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC

Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: arria10: Add qts-filter for Arria10 socfpga
Dalon Westergreen [Sat, 28 Sep 2019 01:43:24 +0000 (18:43 -0700)]
arm: socfpga: arria10: Add qts-filter for Arria10 socfpga

Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.

Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Disable CONFIG_PSCI_RESET
Chee Hong Ang [Fri, 14 Aug 2020 03:07:23 +0000 (11:07 +0800)]
arm: socfpga: soc64: Disable CONFIG_PSCI_RESET

Don't invoke 'SYSTEM_RESET' PSCI function because PSCI
function calls are not supported by u-boot running in EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Add mailbox retry support
Ley Foon Tan [Wed, 12 Aug 2020 01:56:25 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Add mailbox retry support

Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: mailbox: Update mailbox response codes
Ley Foon Tan [Wed, 12 Aug 2020 01:56:24 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Update mailbox response codes

Sync latest mailbox response codes from SDM firmware.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: mailbox: Support sending large mailbox command
Chee Hong Ang [Wed, 12 Aug 2020 01:56:23 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Support sending large mailbox command

Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Always read mailbox responses before returning status
Chee Hong Ang [Wed, 12 Aug 2020 01:56:22 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Always read mailbox responses before returning status

Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: mailbox: Refactor mailbox timeout event handling
Chee Hong Ang [Wed, 12 Aug 2020 01:56:21 +0000 (09:56 +0800)]
arm: socfpga: mailbox: Refactor mailbox timeout event handling

Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Document down boot_scratch_cold register usage
Chin Liang See [Mon, 10 Aug 2020 02:55:56 +0000 (10:55 +0800)]
arm: socfpga: soc64: Document down boot_scratch_cold register usage

Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Add timeout waiting for NOC idle ACK
Chee Hong Ang [Mon, 10 Aug 2020 14:59:49 +0000 (22:59 +0800)]
arm: socfpga: soc64: Add timeout waiting for NOC idle ACK

Add timeout waiting for NOC idle ACK during FPGA bridge
disable/enable.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoarm: socfpga: agilex: Enable FPGA Full Reconfiguration support
Chee Hong Ang [Fri, 7 Aug 2020 03:50:05 +0000 (11:50 +0800)]
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support

Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agofpga: intel_sdm_mb: Add watchdog reset
Chee Hong Ang [Fri, 7 Aug 2020 03:50:04 +0000 (11:50 +0800)]
fpga: intel_sdm_mb: Add watchdog reset

Ensure watchdog reset is not triggered if the fpga
reconfiguration is taking too long.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agofpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox
Chee Hong Ang [Fri, 7 Aug 2020 03:50:03 +0000 (11:50 +0800)]
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox

Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: Use DM watchdog timer
Chee Hong Ang [Thu, 6 Aug 2020 04:15:33 +0000 (12:15 +0800)]
arm: socfpga: Use DM watchdog timer

All SoCFPGA platforms (except Cyclone V) are now switching
to CONFIG_WDT (driver model for watchdog timer drivers)
from CONFIG_HW_WATCHDOG.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Show reset state in SPL
Chee Hong Ang [Wed, 5 Aug 2020 13:15:57 +0000 (21:15 +0800)]
arm: socfpga: soc64: Show reset state in SPL

Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Add SDM triggered warm reset bit mask
Chee Hong Ang [Wed, 5 Aug 2020 13:15:56 +0000 (21:15 +0800)]
arm: socfpga: soc64: Add SDM triggered warm reset bit mask

Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat
register when checking for HPS warm reset status.
Refactor the warm reset mask macro for clarity purpose.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agosysreset: socfpga: agilex: Enable sysreset support
Chee Hong Ang [Wed, 5 Aug 2020 12:11:26 +0000 (20:11 +0800)]
sysreset: socfpga: agilex: Enable sysreset support

Enable sysreset support for Agilex platform.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agosysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64
Chee Hong Ang [Wed, 5 Aug 2020 12:11:25 +0000 (20:11 +0800)]
sysreset: socfpga: soc64: Rename SYSRESET SoCFPGA driver for S10 to SoC64

Rename the driver from S10 to SoC64 because Intel Agilex platform
also using the this SYSRESET SoCFPGA driver for S10.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoconfigs: socfpga: soc64: Avoid SPL enter infinite loop during exception
Chin Liang See [Wed, 5 Aug 2020 10:34:33 +0000 (18:34 +0800)]
configs: socfpga: soc64: Avoid SPL enter infinite loop during exception

In current implementation, any exception would trigger a CPU reset.
But a bad written SPL would cause infinite loop where the system
will reload the same SPL instead of loading factory safe image.

Hence this patch is to ensure any exception will cause a hang. At this
moment, watchdog shall be triggered and Remote System Update mechanism
shall load the next production image or factory safe image.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Initialize timer in SPL only
Chee Hong Ang [Fri, 10 Jul 2020 15:53:13 +0000 (23:53 +0800)]
arm: socfpga: soc64: Initialize timer in SPL only

Timer only need to be initialized once in SPL.
This patch remove the redundancy of initializing the
timer again in U-Boot proper

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoarm: socfpga: soc64: Remove PHY interface setup from misc arch init
Chee Hong Ang [Fri, 10 Jul 2020 15:52:32 +0000 (23:52 +0800)]
arm: socfpga: soc64: Remove PHY interface setup from misc arch init

'dwmac_socfpga' driver will setup the PHY interface during probe.
PHY interface setup in arch_misc_init() is no longer needed.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoclk: agilex: Additional membus writes for HPS PLL
Chee Hong Ang [Fri, 10 Jul 2020 12:55:23 +0000 (20:55 +0800)]
clk: agilex: Additional membus writes for HPS PLL

Add additional membus writes to configure main and peripheral PLL
for Agilex's clock manager.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
4 years agoclk: agilex: Handle clock configuration differently in SPL and U-Boot proper
Chee Hong Ang [Fri, 10 Jul 2020 12:55:22 +0000 (20:55 +0800)]
clk: agilex: Handle clock configuration differently in SPL and U-Boot proper

Since warm reset may optionally set the CLock Manager to'boot mode',
the clock driver should always force the Agilex's Clock Manager to
'boot mode' before the clock driver start configuring the Clock Manager
in SPL.
In SSBL, clock driver will skip the Clock Manager configuration
if it's already being setup by SPL (Clock Manager NOT in 'boot
mode') to prevent any inaccurate clocking issues happened on HPS
peripherals such as UART, MAC and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoclk: agilex: Add clock enable support
Ley Foon Tan [Fri, 10 Jul 2020 12:55:21 +0000 (20:55 +0800)]
clk: agilex: Add clock enable support

Some drivers probing failed if clock enable function is not supported in
clock driver. So, add clock enable function to clock driver to solve it.

Return 0 (success) for *.enable function because all clocks are enabled
by default in clock driver probe.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoclk: agilex: Add NAND clock support
Ley Foon Tan [Fri, 10 Jul 2020 12:55:20 +0000 (20:55 +0800)]
clk: agilex: Add NAND clock support

Add get nand_clk and nand_x clock support.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
4 years agoqemu-arm64: Enable POSITION_INDEPENDENT
Andre Przywara [Wed, 30 Sep 2020 16:39:18 +0000 (17:39 +0100)]
qemu-arm64: Enable POSITION_INDEPENDENT

Now that PIE works when U-Boot is started from ROM, let's enable
CONFIG_POSITION_INDEPENDENT, which allows to load U-Boot also via
ARM Trusted-Firmware's fip.bin to DRAM, without tweaking the
configuration.

To get a writable initial stack, we need to keep the fixed initial
stack pointer, which points to DRAM in our case.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
4 years agoqemu-arm: Drop ARCH_SUPPORT_TFABOOT
Andre Przywara [Wed, 30 Sep 2020 16:39:17 +0000 (17:39 +0100)]
qemu-arm: Drop ARCH_SUPPORT_TFABOOT

CONFIG_ARCH_SUPPORT_TFABOOT was used on the qemu-arm64 platform to
guard a tweak to the flash bank configuration. U-Boot now reads the
current flash setup from the devicetree, so there is no need for
this option anymore.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoqemu-arm: Remove need to specify flash banks
Andre Przywara [Wed, 30 Sep 2020 16:39:16 +0000 (17:39 +0100)]
qemu-arm: Remove need to specify flash banks

Currently we hard-code the number and initial addresses of QEMU's flash
banks, even though our code is perfectly able to gather the same
information from the DTB provided by QEMU.
This is especially annoying, since we have two slightly different
U-Boot configurations ("bare-metal" vs. loaded via Arm Trusted
Firmware), which need to be selected at build time.

Drop the two hard coded alternatives, and use
CONFIG_SYS_MAX_FLASH_BANKS_DETECT instead, which relies on the DTB to
figure out the actual flash configuration at runtime.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
4 years agoarm64: PIE: Allow fixed stack pointer
Andre Przywara [Wed, 30 Sep 2020 16:39:15 +0000 (17:39 +0100)]
arm64: PIE: Allow fixed stack pointer

Currently selecting CONFIG_POSITION_INDEPENDENT also forces us to use an
initial stack pointer relative to the beginning of the BSS section.
This makes some sense, because this should be writable memory anyway.

However the BSS section is not cleared or used until later in the
setup process (after relocation), so memory nearby might not be
available early enough to host the initial stack. This is an issue if
U-Boot is loaded from (Flash-)ROM, for instance.

Allow CONFIG_INIT_SP_RELATIVE to be turned off by a board's config, to
be able to select a fixed stack pointer, for instance in known good
DRAM.

This will help QEMU utilising PIE, when it's loaded to (Flash-)ROM.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
4 years agoarm64: PIE: Skip fixups if distance is zero
Andre Przywara [Wed, 30 Sep 2020 16:39:14 +0000 (17:39 +0100)]
arm64: PIE: Skip fixups if distance is zero

When the actual offset between link and runtime address is zero, there
is no need for patching up U-Boot early when running with
CONFIG_POSITION_INDEPENDENT.

Skip the whole routine when the distance is 0.

This helps when U-Boot is loaded into ROM, or in otherwise sensitive
memory locations.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
4 years agoarm64: PIE: Do not skip static relocation
Andre Przywara [Wed, 30 Sep 2020 16:39:13 +0000 (17:39 +0100)]
arm64: PIE: Do not skip static relocation

When we build an arm64 target and enable POSITION_INDEPENDENT, we were
skipping our build-time dynamic relocation fixup routine (STATIC_RELA).

This was probably done because we didn't need it in this case, as the
PIE fixup routine in start.S would take care of that at runtime.

However when we now skip this routine (upon detecting that the fixup
offset is 0), this might lead to uninitialised pointers.

Remove the exception, so that we always do the build-time relocation.

NOTE: GNU binutils starting with v2.27.1 do this build-time relocation
automatically, to be in-line with other architecures. So on newer
toolchains our manual fixup is actually not needed. It doesn't hurt to
have it, though, so that we keep compatibility with the popular Linaro
toolchains, which lack this feature.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
4 years agoarm: Kconfig: Explain TFABOOT
Andre Przywara [Wed, 30 Sep 2020 14:45:07 +0000 (15:45 +0100)]
arm: Kconfig: Explain TFABOOT

The CONFIG_TFABOOT option is more about what U-Boot DOES NOT need to do
than to support some features.

Explain a bit more in the Kconfig help text to avoid misunderstandings.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
4 years agoexamples: make examples/ optional
Heinrich Schuchardt [Wed, 23 Sep 2020 17:09:51 +0000 (19:09 +0200)]
examples: make examples/ optional

Most users don't need the standalone API examples. Distributions like SUSE
do not supply libgcc for cross-compiling and we cannot do without on ARMv8
for building examples/.

Make examples selectable via symbol CONFIG_EXAMPLES. It defaults to
yes on ARCH_QEMU to ensure that we compile the API as part of our
continuous integration.

Cc: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
4 years agowdt: designware: fix timeout calculation due to expecting KHz
Jack Mitchell [Thu, 17 Sep 2020 09:30:40 +0000 (10:30 +0100)]
wdt: designware: fix timeout calculation due to expecting KHz

The timeout calculation is based on the clk being in KHz but
the clk api returns the clk value in Hz. Convert this to KHz
to calculate the correct timeout value.

Signed-off-by: Jack Mitchell <ml@embed.me.uk>
4 years agoriscv: Add FPIOA and GPIO support for Kendryte K210
Sean Anderson [Mon, 14 Sep 2020 15:02:06 +0000 (11:02 -0400)]
riscv: Add FPIOA and GPIO support for Kendryte K210

This patch adds the necessary configs and docs for FPIOA and GPIO support
on the K210.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
4 years agoriscv: add DT binding for BOOT button on Maix board
Heinrich Schuchardt [Mon, 14 Sep 2020 15:02:05 +0000 (11:02 -0400)]
riscv: add DT binding for BOOT button on Maix board

Add a device tree binding for the BOOT button on the Maix board.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>