Philippe Reynes [Wed, 14 Nov 2018 12:51:05 +0000 (13:51 +0100)]
test: vboot: clean its file
This update the its file used in vboot test to respect the new
node style name defined in doc/uImage.FIT (for example: replace
kernel@1 by kernel and fdt@1 by fdt-1)
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Philippe Reynes [Wed, 14 Nov 2018 12:51:00 +0000 (13:51 +0100)]
rsa: add a structure for the padding
The rsa signature use a padding algorithm. By default, we use the
padding pkcs-1.5. In order to add some new padding algorithm, we
add a padding framework to manage several padding algorithm.
The choice of the padding is done in the file .its.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Philippe Reynes [Wed, 14 Nov 2018 12:50:59 +0000 (13:50 +0100)]
rsa: use new openssl API to create signature
Previous implementation of the rsa signature was using
the openssl API EVP_Sign*, but the new openssl API
EVP_DigestSign* is more flexible. So we move to this
new API.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Alexey Brodkin [Tue, 27 Nov 2018 06:46:59 +0000 (09:46 +0300)]
arc: emsdp: Read real CPU clock value from hardware
We do real CPU clock measurement with help of built-in
counters. Thus we may accommodate different real clock values
that appear in different FPA images instead of relying on
something hard-coded in the .dtb.
And while at it make make SDIO base address define
look similar to others with casting to "(void *)".
Alexey Brodkin [Tue, 27 Nov 2018 06:46:57 +0000 (09:46 +0300)]
ARC: Improve identification of ARC cores
1. Try to guess a ARC core template that was used
i.e. not just name a core family but something more
menaingful like "ARC HS38", "ARC EM11D" etc.
We do it checking availability of the key differentiation
features like:
- Caches (we actually only check for L1 I$ fpr simplicity)
- XY-memory
- DSP extensions etc.
Alexey Brodkin [Tue, 27 Nov 2018 06:20:44 +0000 (09:20 +0300)]
arc: emsdp: Bump RAM size to 16 Mb
On v2 boards that will hit real stock we'll have 16 Mb of RAM.
Note on v1 boards (if anybody ever get one out of trash bin)
this leads to U-Boot execution freeze in the middle ofthe relocation
so don't be surprised.
drivers: rtc: correctly convert seconds to time structure
Variable 'days' must be defined as signed int. Otherwise the conversion
fails for some dates, e.g. 2004-08-25. Cf function rtc_time64_to_tm() in
the Linux kernel source.
Fixes: 992c1db45591 "drivers: rtc: resolve year 2038 problem in rtc_to_tm" Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Sat, 1 Dec 2018 19:17:27 +0000 (14:17 -0500)]
Merge tag 'for-master-20181130' of git://git.denx.de/u-boot-rockchip
Improvements:
- RK3188 USB-UART functionality
- errors triggering a hard-stop in SPL on the RK3399 are reported
- Rockchip RV1108 (SoC) support
- MicroCrystal RV3029 (RTC) DM driver
Fixes:
- RK3188 early UART setup
- limit SD-card frequency to 40MHz on the RK3399-Q7
- MIPI fixes
- RK3399 CPUB clock initialisation
Tom Rini [Fri, 30 Nov 2018 22:09:50 +0000 (17:09 -0500)]
Merge tag 'pull-30nov18' of git://git.denx.de/u-boot-dm
Fix sound on sandbox
Convert TPM fully to DM
Tidy up sandbox I2C emulation
Add a 'make qcheck' target for faster testing
A few other misc things
(dropped the final patch which breaks clang for some reason)
Philipp Tomsich [Tue, 27 Nov 2018 21:53:58 +0000 (22:53 +0100)]
rtc: rv3029: update to support DM and sync with Linux 4.17
The "Flamingo" carrier-board for the RK3399-Q7 has a RV3029 populated
and the application will use the off-module RV3029 RTC including the
battery backed SRAM.
To support this use case, this commit includes the following changes:
* updates the rv3029 driver to use DM
* implements the read8/write8 operations
This syncs the implementation with the Linux code (based on 4.17),
porting the trickle-charger support from there (with improvements to
avoid unnecessary EEPROM updates) and adheres to the Linux DTS
binding.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Otavio Salvador [Fri, 30 Nov 2018 13:34:13 +0000 (11:34 -0200)]
ARM: rockchip: rv1108: Enable BOUNCE_BUFFER
In order to be able to build the Rockchip eMMC driver on rv1108, the
BOUNCE_BUFFER option needs to be selected. Select it like it is done
on the other Rockchip SoC common files.
Reviewed-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Fri, 30 Nov 2018 17:58:58 +0000 (18:58 +0100)]
rockchip: rk3399-puma: reduce sd card max-frequency to 40MHz
Some SanDisk Ultra cards trigger intermittent errors on detection
resulting in an -EOPNOTSUPP, when running at 50MHz.
Waveform analysis suggest that the level shifters that are used on the
RK3399-Q7 module (for voltage translation between the on-module
voltages and the 3.3V required on the card-edge) don't handle clock
rates at or above 48MHz properly. This change reduces the maximum
frequency on the external SD-interface to 40MHz (for a safety margin
of 20%).
Reported-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Kever Yang [Thu, 29 Nov 2018 01:59:41 +0000 (09:59 +0800)]
rockchip: rock: remove TPL_TINY_MEMSET
The RK3188 rock board does not need TPL: remove TPL_TINY_MEMSET from
config.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up commit message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Mon, 19 Nov 2018 12:03:51 +0000 (13:03 +0100)]
rockchip: rk3399: spl: always report errors triggering a hard stop
The RK3399 SPL has two cases that may end in a hard-stop: if either
the pinctrl can not be initialised or if the DRAM fails to initialise.
Both have previously not triggered an error message unless DEBUG was
defined (i.e. both used debug() to print the error).
This converts both error messages to be printed using pr_err() to
ensure that some output points to the cause of the hard-stop.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Richard Röjfors [Wed, 14 Nov 2018 13:13:53 +0000 (14:13 +0100)]
rockchip: video: mipi: Fix phy frequency setting
There was an incorrect check when looping and finding the first
fast enough frequency in the freq_rang table. The code did
actually return the first that was either exactly correct or
too slow.
Signed-off-by: Richard Röjfors <richard@puffinpack.se> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Heiko Stuebner [Mon, 8 Oct 2018 11:01:57 +0000 (13:01 +0200)]
rockchip: rk3188: fix early uart setup
Commit 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions
into pinctrl-driver") moved the iomux settings out of the grf header
to prevent conflicts with the iomux definitions of other rockchip socs.
This also breaks the early uart setup, as the iomux for uart2 are needed.
To fix that just put the tiny amount of needed iomux definitions next to
the early uart code.
Fixes: 7a6d7d3e1279 ("rockchip: pinctrl: rk3188: Move the iomux definitions into pinctrl-driver") Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Heiko Stuebner [Mon, 8 Oct 2018 11:01:56 +0000 (13:01 +0200)]
rockchip: rk3188: add support for usb-uart functionality
Rockchip socs can route the debug uart pins through the d+ and d- pins
of one specific usbphy per soc. Add a config option and implement the
setting on the rk3188.
Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed up to mark grf as maybe unused:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Stefan Roese [Fri, 30 Nov 2018 06:46:30 +0000 (07:46 +0100)]
mips: mt76xx: gardena-smart-gateway: Add factory data variable handling
Some factory data is stored in the SPI NOR and needs to get extracted
from there into U-Boot environment variables.
This patch also includes a board-specific command "fd_write" to
provide some dummy / default values for this factory-data in the SPI
NOR flash. This should only be necessary for testing purposes though.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tom Rini [Fri, 30 Nov 2018 16:20:03 +0000 (11:20 -0500)]
Merge git://git.denx.de/u-boot-marvell
- Some Kirkwood boards converted to DM_SPI by Chris
- New Armada-385 SoC revision printed by Chris
- Ethernet enable on mcbin by Baruch
- Support 2 DRAM banks on Armada-8k boards by Baruch
Chris Packham [Tue, 27 Nov 2018 21:32:00 +0000 (10:32 +1300)]
ARM: mvebu: add revision id for Armada-385 B0
Marvell have release a B0 revision of the Armada-385 SoC. This fixes a
hardware errata enabling RGMII to work when the Ethernet voltage is
configured to 3.3V.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Baruch Siach [Wed, 21 Nov 2018 07:59:32 +0000 (09:59 +0200)]
arm: mvebu: configs: armada8k: use 2 DRAM banks
Commit 2b4d964718c0 ("arm64: mvebu: a8k: autodetect RAM size") added an
ATF query to get the detected RAM size on Armada 8K platforms. To be
usable we must have 2 DRAM banks. Set Armada 8K configurations to 2
banks.
Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Keerthy [Mon, 19 Nov 2018 06:14:47 +0000 (11:44 +0530)]
core: ofnode: Fix ofnode_get_addr_index function
Currently the else part of ofnode_get_addr_index function
does not fetch addresses based on the index but rather just
returns the base address. Fix that.
Simon Glass [Sun, 18 Nov 2018 21:22:27 +0000 (14:22 -0700)]
tpm: Convert to use a device parameter
At present many TPM calls assume there is only one TPM in the system and
look up this TPM themselves. This is inconsistent with driver model, which
expects all driver methods to have a device parameter. Update the code to
correct this.
Simon Glass [Sun, 18 Nov 2018 21:22:26 +0000 (14:22 -0700)]
tpm: Export the open/close functions
At present these functions are not accessible outside the TPM library, but
in some cases we need to call them. Export them in the header file and add
a define for the SHA1 digest size.
Also adjust tpm_open() to call tpm_close() first so that the TPM is in a
known state before opening (e.g. by a previous phase of U-Boot).
Simon Glass [Tue, 13 Nov 2018 22:55:20 +0000 (15:55 -0700)]
sandbox: Use memmove() to move overlapping regions
The use of strcpy() to remove characters at the start of a string is safe
in U-Boot, since we know the implementation. But in os.c we are using the
C library's strcpy() function, where this behaviour is not permitted.
Update the code to use memmove() instead.
Reported-by: Coverity (CID: 173279) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexander Graf <agraf@suse.de>
Simon Glass [Fri, 16 Nov 2018 02:56:14 +0000 (19:56 -0700)]
sound: sandbox: Use the correct frequency
At present we request a particular frequency but we may not get the exact
same frequency in response. So use the actual frequency for generation of
the square wave. This ensures that the pitch remains accurate on all host
machines.
Simon Glass [Fri, 16 Nov 2018 02:56:13 +0000 (19:56 -0700)]
sound: Add sample rate as a parameter for square wave
At present this value is hard-coded in the function that generates a
square wave. Since sample rates vary between different hardware, it makes
more sense to have this as a parameter.
In this case the emulation device is attached to i2c bus on address 0x43
and provides the Real-Time-Clock (RTC) functionality.
However this is not ideal, since every device on an I2C bus has a child
device. This is only really the case for sandbox, but we want to avoid
special-case code for sandbox.
A better approach seems to be to add a separate node on the bus, an
'emulation parent'. This can be given a bogus address (such as 0xff) and
hides all the emulators away. Then we can use a phandle to point from the
device to the correct emualtor, and only on sandbox. The code to find an
emulator does not interfere with normal i2c operation.
Add a new UCLASS_I2C_EMUL_PARENT uclass which allows finding an emulator
given a bus, and finding a bus given an emulator. This will be used in a
follow-on patch.
Simon Glass [Sun, 18 Nov 2018 15:14:32 +0000 (08:14 -0700)]
dm: core: Put UCLASS_SIMPLE_BUS in order
This is currently at the top in the space for internal use. But this
uclass is used outside driver model and test code. Move it into the
correct alpha order.
Simon Glass [Sun, 18 Nov 2018 15:14:31 +0000 (08:14 -0700)]
dm: core: Add a few more specific child-finding functions
Add two functions which can find a child device by uclass or by name.
The first is useful with Multi-Function-Devices (MFDs) to find one of a
particular type. The second is useful when only the name is known.
Simon Glass [Sun, 18 Nov 2018 15:14:29 +0000 (08:14 -0700)]
test: Add a 'make qcheck' target for quicker testing
At present tests are quite slow to run, over a minute on my machine. This
presents a considerable barrier to bisecting for failures.
The slowest tests are the filesystem ones and the buildman --fetch-arch
test. Add a new 'qcheck' target that skips these tests. This reduces test
time down to about 40 second, still too long, but bearable.
dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)
Adapt board dts files that are not in Linux to keep their old
behaviour.
Change licenses to SPDX.
(Patman warnings/errors are in 1:1 copied files from Linux)
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
gpio: dwapb_gpio: fix binding without bank-name property
As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.
This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.
This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.
The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Ryder Lee [Thu, 15 Nov 2018 02:08:02 +0000 (10:08 +0800)]
serial: MediaTek: add high-speed uart driver for MediaTek SoCs
Many SoCs from MediaTek have a high-speed uart. This UART is compatible
with the ns16550 in legacy mode. It has extra registers for high-speed
mode which can reach a maximum baudrate at 921600.
However this UART will no longer be compatible if it's in high-speed mode.
Some BootROM of MediaTek's SoCs will change the UART into high-speed mode
and the U-Boot must use this driver to initialize the UART.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Tested-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:08:00 +0000 (10:08 +0800)]
power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:07:58 +0000 (10:07 +0800)]
pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Ryder Lee [Thu, 15 Nov 2018 02:07:54 +0000 (10:07 +0800)]
clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
projects / u-boot.git / log