Fabio Estevam [Thu, 14 Feb 2019 13:37:51 +0000 (11:37 -0200)]
warp7: Fix the write to the LDOGCTL PMIC register
The third parameter of the pmic_clrsetbits() function is the mask
to the register and the correct mask is 1 not 0.
Since the LDOGCTL only contains a single valid bit (bit 0),
we can use pmic_reg_write() and write 1 directly, which fixes
the problem in a simpler way and use the original pmic function
that was used prior to the DM PMIC conversion.
Marcin Niestroj [Sat, 19 Jan 2019 16:06:46 +0000 (17:06 +0100)]
ARM: liteboard: move towards driver model and device-tree boot
This patch mostly enables DM drivers in board defconfig and all their
dependencies. Additionally we remove USB code that is on longer
executed after enabling CONFIG_DM_USB. Enable CONFIG_PINCTRL, so we
can get rid of ethernet pin configuration.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Chris Spencer [Mon, 4 Feb 2019 10:05:34 +0000 (10:05 +0000)]
imx8mq_evk_defconfig: Enable pinctrl driver
The Ethernet controller is not able to initialise correctly without the
pinctrl driver.
This config setting was enabled in the initial version of this file,
but was removed by a savedefconfig resync because the parameter did not
actually exist at that point.
Fixes: 1bac199e8c87 ("configs: Resync with savedefconfig") Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk> Reviewed-by: Fabio Estevam <festevam@gmail.com>
Bin Meng [Tue, 26 Feb 2019 09:52:19 +0000 (01:52 -0800)]
x86: Make sure i8254 is setup correctly before generating beeps
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Andy Shevchenko [Thu, 28 Feb 2019 08:10:07 +0000 (10:10 +0200)]
x86: edison: Add the rest of UARTs present on board
Intel Edison has three UART ports, i.e.
port 0 - Bluetooth
port 1 - auxiliary, available for general purpose use
port 2 - debugging, usually console output is here
Enable all of them for future use.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 28 Feb 2019 15:19:54 +0000 (17:19 +0200)]
x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.
For example, on properly described Intel Edison board the console UART
is a third one.
Use current serial device as described in global data.
Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API") Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Vasut [Sat, 9 Mar 2019 20:58:09 +0000 (21:58 +0100)]
ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Sat, 9 Mar 2019 20:57:58 +0000 (21:57 +0100)]
ddr: socfpga: Clean up EMIF reset
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Fri, 8 Mar 2019 18:11:55 +0000 (19:11 +0100)]
ddr: socfpga: Fix EMIF clear timeout
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.
This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Wed, 6 Mar 2019 19:07:55 +0000 (20:07 +0100)]
ARM: socfpga: Fix A10 SoCDK Kconfig
The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
checking for specific board configuration, which works with one
single platform in tree, but not with multiple. Fix it.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Dinh Nguyen [Sun, 3 Mar 2019 17:02:10 +0000 (11:02 -0600)]
ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Eugeniu Rosca [Sat, 9 Mar 2019 13:04:57 +0000 (14:04 +0100)]
ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
v2019.01 commit cbff9f80cedd ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.
Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
- f529bc551b6d ("ARM: dts: rmobile: Extract USB nodes on M3N")
- 830b94f76867 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")
Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
- not needed if no U-boot-specific changes are needed in those nodes.
- potentially dangerous/error-prone, since the duplicated properties
override the properties originally defined in <soc>.dtsi. One
possible consequence is that <soc>.dtsi is getting an update from
Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
the obsolete property values from <soc>-u-boot.dtsi will take
precedence masking some of the <soc>.dtsi updates, potentially
leading to all kind of obscure issues.
Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).
What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.
The update didn't fully work on R-Car3 due to the
CONFIG_SYS_BOOTMAPSZ=8MiB definition left by v2016.09 commit e525d34b476e ("ARM: rmobile: Add support salvator-x board"),
which is explained in below README excerpt:
----8<----
CONFIG_SYS_BOOTMAPSZ:
[..] If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
----8<----
Allow the original commit to accomplish its purpose on R-Car3 targets
by removing the CONFIG_SYS_BOOTMAPSZ definition.
Jagan Teki [Wed, 27 Feb 2019 18:56:57 +0000 (00:26 +0530)]
clk: sunxi: Implement EMAC, GMAC clocks, resets
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tom Rini [Fri, 8 Mar 2019 23:04:13 +0000 (18:04 -0500)]
Merge branch '2019-03-08-master-imports'
- Assorted minor fixes:
- ARM: qemu-arm: enable USB boot in distro boot with UEFI
- image: fdt: handle coalesced reserve region
- cmd: thordown: Fix spelling of download.
- fdt: Fix FIT header verification in mkimage and conduct same checks
as bootm
- test: Update test-imagetools.sh to match new syntax
Handle in boot_fdt_reserve_region
any return value > 0 of lmb_reserve() function;
it occurs when coalesced region are found:
adjacent reserved region are merged.
This patch avoid the error trace:
ERROR: reserving fdt memory region failed..
when reserved region are merged (return value = 1).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Martyn Welch [Thu, 14 Feb 2019 13:11:35 +0000 (13:11 +0000)]
test: Update test-imagetools.sh to match new syntax
The syntax of dumpimage was simplified in commit 12b831879a76 ("tools:
dumpimage: Simplify arguments"), but the test
(test/image/test-imagetools.sh) was not updated and is now failing.
Ondrej Jirman [Wed, 13 Feb 2019 17:51:05 +0000 (18:51 +0100)]
power: axp818: Fix typo in axp_set_dldo
Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL
register to configure the voltage instead of setting AXP818_ELDO1_CTRL
register which is obviously incorrect.
Signed-off-by: Ondřej Jirman <megous@megous.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
i2c: i2c_cdns: Add support for handling arbitration lost
This patch adds support for handling arbitration lost
in case of multi master mode. When an arbitration lost
is detected, it retries for 10 times before failing.
The arbitration lost interrupt was not getting cleared
while clearing interrupts. This patch fixes this by adding
arbitration lost interrupt as well during clear. This patch
also removes hardcoded value and defined a macro for it.
Marek Vasut [Thu, 7 Mar 2019 02:41:08 +0000 (03:41 +0100)]
i2c: rcar_iic: Read ICSR only once
Read ICSR only once to avoid missing interrupts. This happens on R8A7791
Porter during reset, when reading the PMIC register 0x13, which may fail
sometimes because of the missed DTE interrupt.
Tom Rini [Mon, 4 Mar 2019 18:05:53 +0000 (13:05 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
Jagan Teki [Wed, 27 Feb 2019 14:32:13 +0000 (20:02 +0530)]
spi: Rename sun4i_spi.c into spi-sunxi.c
Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.
Also update the function, variable, structure names in driver from
sun4i into sunxi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:12 +0000 (20:02 +0530)]
spi: sun4i: Driver cleanup
- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
places to add platdata support in future.
- use sentinel sun4i_spi_ids.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:11 +0000 (20:02 +0530)]
spi: sun4: Add A31 spi controller support
The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.
So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:10 +0000 (20:02 +0530)]
spi: sun4i: Add CLK support
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.
So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.
This patch would also do that change, by enable and disable clock in
proper order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:09 +0000 (20:02 +0530)]
spi: sun4i: Support fifo_depth via drvdata
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:08 +0000 (20:02 +0530)]
spi: sun4i: Access registers and bits via enum offsets
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.
Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.
Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
Jagan Teki [Wed, 27 Feb 2019 14:32:06 +0000 (20:02 +0530)]
clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:05 +0000 (20:02 +0530)]
spi: sun4i: Poll for rxfifo to be filled up
To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.
To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.
So, add code for polling rxfifo to be filled up using fifo
status register.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.
The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Eugen Hristev [Fri, 8 Feb 2019 08:57:01 +0000 (10:57 +0200)]
configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs
SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND
information. The initial stage 1 bootloader will use this header in case the
NAND flash doesn't support commands to retrieve sector size, etc.
However this header is bad for different boot media, like MMC or SPI.
In case SD_BOOT or SPI_BOOT is used, remove the config for this.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Alexander Dahl [Wed, 6 Feb 2019 14:19:41 +0000 (15:19 +0100)]
configs: sama5d27_som1_ek: Activate misc init for uSD variant
This was already set for 'sama5d27_som1_ek_mmc_defconfig' (first SD
card, full size). Without this option set, the MAC address is not read
from the I²C EEPROM at boot, and remains unset:
U-Boot 2019.01 (Jan 01 2019 - 00:00:00 +0000)
CPU: SAMA5D27 1G bits DDR2 SDRAM
Crystal frequency: 24 MHz
CPU clock : 492 MHz
Master clock : 164 MHz
DRAM: 128 MiB
MMC: sdio-host@a0000000: 0, sdio-host@b0000000: 1
Loading Environment from FAT... OK
In: serial
Out: serial
Err: serial
Net:
Error: ethernet@f8008000 address not set.
eth-1: ethernet@f8008000
Hit any key to stop autoboot: 0
pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.
pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_x
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.
pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndf
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.
pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795
/ r8a7796 / r8a77965. This information was confirmed in the R-Car
Gen3 Hardware Manual Rev.1.50.
pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adg
This patch fixes to the correct names, and "_" is not include after
"adg" for r8a7795/r8a7796/r8a77965. This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.
pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03",
and "HDMI0_CEC" to "GP7_02". This information was confirmed in the
R-Car Gen3 Hardware Manual Rev.1.50.
Laurentiu Tudor [Tue, 26 Feb 2019 11:18:34 +0000 (13:18 +0200)]
armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:
WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.
Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.
Laurentiu Tudor [Tue, 26 Feb 2019 11:18:33 +0000 (13:18 +0200)]
armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.
Laurentiu Tudor [Tue, 26 Feb 2019 11:18:32 +0000 (13:18 +0200)]
fsl_sec: fix register layout on Layerscape architectures
On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.
projects / u-boot.git / log