Simon Glass [Fri, 12 Aug 2022 01:34:57 +0000 (19:34 -0600)]
blk: Rewrite if_type to name functions
These are currently using a simple array lookup in one direction, and
relying on if_type being sequential.
With the move to uclass IDs this needs to change. Update the code to
prepare for the new way. This patch is intended to introduce no
functional change.
The returning of "(none)" from blk_get_if_type_name() is handling a case
that should not happen in either case.
Simon Glass [Fri, 12 Aug 2022 01:34:51 +0000 (19:34 -0600)]
blk: Hide the BLK and SPL_LEGACY_BLOCK options
We don't want boards to be able to change these. They can be handled
as dependencies of options that need them, such as SPL_MMC. There is no
point in enabling the block interface without any storage devices to
create a block device.
Hide both options from the 'menuconfig' display and deny their use in
defconfig files.
Simon Glass [Fri, 12 Aug 2022 01:34:48 +0000 (19:34 -0600)]
blk: Rename HAVE_BLOCK_DEVICE
This option is fact really related to SPL. For U-Boot proper we always use
driver model for block devices, so CONFIG_BLK is enabled if block devices
are in use.
It is only for SPL that we have two cases:
- SPL_BLK is enabled, in which case we use driver model and blk-uclass.c
- SPL_BLK is not enabled, in which case (if we need block devices) we must
use blk_legacy.c
Rename the symbol to SPL_LEGACY_BLOCK to make this clear. This is
different enough from BLK and SPL_BLK that there should be no confusion.
Simon Glass [Fri, 12 Aug 2022 01:34:46 +0000 (19:34 -0600)]
cmd: Drop use of HAVE_BLOCK_DEVICE
This condition is not needed for these commands, since BLK is enabled for
all boards which use block devices and commands are not available in SPL,
so even if SPL_BLK is not enabled, it doesn't affect commands.
Simon Glass [Fri, 12 Aug 2022 01:34:45 +0000 (19:34 -0600)]
blk: Use a function for whether block devices are available
At present we use HAVE_BLOCK_DEVICE to indicate when block devices are
available.
This is a very strange option, since it partially duplicates the BLK
option used by driver model. It also covers both U-Boot proper and SPL,
even though one might have block devices and another not.
As a first step towards correcting this, create a new inline function
called blk_enabled() which indicates if block devices are available.
This cannot be used in Makefiles, or #if clauses, but can be used in C
code.
A function is useful because we cannot use CONFIG_IS_ENABLED(BLK) to
decide if block devices are needed, since we must consider the legacy
block interface, enabled by HAVE_BLOCK_DEVICE
Update a few places where it can be used and drop some unnecessary #if
checks around some functions in disk/part.c - rely on the compiler's
dead-code elimination instead.
Simon Glass [Fri, 12 Aug 2022 01:34:44 +0000 (19:34 -0600)]
disk: Use Makefile to omit partition drivers
At present these files have an #ifdef covering the whole file. Move the
condition to the Makefile instead.
Add BLK to the condition since future patches will adjust things so that
HAVE_BLOCK_DEVICE is only for SPL, but the partition drivers are needed
in U-Boot proper too.
Simon Glass [Fri, 12 Aug 2022 01:34:42 +0000 (19:34 -0600)]
ata: Fix an instance of SPL_SATA_SUPPORT
The _SUPPORT suffix should be dropped. This happened because the rename
was applied around the same time as this new option, so did not include
renaming the new option.
The relevant commits are:
f7560376ae sata: Rename SATA_SUPPORT to SATA 73059529b2 ata: ahci-pci: Add new option CONFIG_SPL_AHCI_PCI
Nokia RX-51: Fix documentation how to enable UBI support
Disable UBI fastmap support which is not supported by original Maemo 5
kernel and explicitly set UBI BEB limit to 10%, which is the value used by
original Maemo 5 kernel. U-Boot default value is 20%.
Nokia RX-51: Change UBIFS volume size to 1870 LEBs in test script
Original Nokia UBIFS system image has 1870 LEBs, so set UBIFS volume size
in test script to the same value. Number of 1870 LEBs corresponds to 230MiB
(LEB size * num of LEBs = 126KiB * 1870 = 230MiB).
Nokia RX-51: Set default SYS_LOAD_ADDR to 0x80008000
At address 0x80000100 are stored initial atags passed to U-Boot by NOLO.
So do not overwrite them when using $loadaddr variable which value is set
from CONFIG_SYS_LOAD_ADDR option.
Nokia RX-51: Do not clear unknown memory in lowlevel_init.S
If kernel image in uImage or zImage format is not detected by
lowlevel_init.S code then do not clear memory location where image was
expected. If image is not detected then this memory region is unknown.
So do not unconditionally clear it.
Jayesh Choudhary [Tue, 30 Aug 2022 10:24:30 +0000 (15:54 +0530)]
configs: Add configs for j721s2 High Security EVM
Add j721s2 High Security EVM defconfig.
These configs are same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_SPL_FIT_IMAGE_POST_PROCESS option set to 'y'
CONFIG_BOOTCOMMAND uses FIT images for booting
Andrew Davis [Tue, 30 Aug 2022 10:24:29 +0000 (15:54 +0530)]
configs: Add configs for J7200 High Security EVM
Add J7200 High Security EVM defconfig.
These defconfigs are the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_BOOTCOMMAND uses FIT images for booting
Signed-off-by: Andrew Davis <afd@ti.com>
[j-choudhary@ti.com: add few configs from GP variant which were missing] Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
brppt1: Update environment to support new boot concept
* Drop legacy /boot/PPTImage.md5 check
* Update device tree naming
* Update t30args#0 root cmd line property to support latest kernel
versions (root=/dev/mmcblk0p2 for linux < 4 and
root=/dev/mmcblk1p2 for linux >= 4)
* Add custom bootloader version string
* Destroy invalid dtb at ${dtbaddr} and configuration script at
${cfgaddr} to ensure proper boot in warm restart case.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Commit 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr")
destroys the boot targets b_t30lgcy#0 and b_t30lgcy#1. The reason behind
this is, that b_t30lgcy#0 and b_t30lgcy#1 both load the for booting
needed device trees from mmc and the cfgscr script patches those. Because
of this, cfgscr is not allowed to destroy the previously loaded device
tree otherwise cfgscr will fail.
This patch moves the device trees invalidation on warm restart to the
PREBOOT cmd to fix that issue.
Fixes: 0ea4fc4dcf90 ("board/BuR: invalidate ${dtbaddr} before cfgscr") Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Commit 6337d53fdf45 ("arm: dts: sync am33xx with Linux 5.9-rc7") syncs
the am335x device tree with the latest linux kernel am335x device tree.
That causes problems with device tree in SPL stage.
To fix the issues CONFIG_SPL_OF_TRANSLATE must be set to handle the
synced bus addresses correctly.
A custom U-Boot device tree is also needed since the SPL build removes
bus properties from bus nodes which are not explicitly marked with the
u-boot,dm-spl or u-boot,dm-pre-reloc flag. Therefore all parent buses of
the in the SPL needed devices must be marked with u-boot,dm-pre-reloc.
Also since there is no driver for "ti,sysc" compatible property in SPL
the buses marked with this compatible string must also be marked with
compatible = "simple-bus" to make the underlying devices visible in
SPL. Otherwise the matching device drivers aren't found and the uclass
drivers are dropped.
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tom Rini [Thu, 15 Sep 2022 13:59:47 +0000 (09:59 -0400)]
Merge branch '2022-09-15-general-improvements' into next
- Add uncompressed kernel image support to falcon mode, TEE
improvements, make xyz-modem timeout configurable, gpio updates and
other assorted improvements.
Check the that the hash length is shorter than the message length. This
avoids:
./tools/../lib/rsa/rsa-verify.c:275:11: warning:
‘*db’ may be used uninitialized [-Wmaybe-uninitialized]
275 | db[0] &= 0xff >> leftmost_bits;
Fixes: 061daa0b61f0 ("rsa: add support of padding pss") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Tue, 30 Aug 2022 20:40:37 +0000 (16:40 -0400)]
cli: Reduce size of readline buffers in SPL
Normally, readline is not used int SPL. However, it may be useful to
enable the Freescale DDR interactive mode in SPL, while U-Boot is still
executing from SRAM. The default settings for readline result in a large
buffer being allocated. Reduce the size of the maximum input line, and
the number of lines of scrollback when building for SPL.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Patrice Chotard [Tue, 30 Aug 2022 12:09:11 +0000 (14:09 +0200)]
gpio: Allow to print pin's label even for pin with GPIOF_FUNC function
Currently, if pin's function is GPIOF_FUNC, only "func" if displayed
without any other information. It would be interesting, if information is
available, to indicate which pinmuxing's name is used.
For example, for STM32 SoC's based platform, "gpio status" command
output :
The nvme driver falsely assumed that the last entry on a page
of the prp-list always points to the next page of the prp-list.
This potentially can lead to the illegal creation of pages on
the prp-list with only a single entry. This change now ensures
that splitting the prp-list into multiple pages, behaves now as
required by the NVME-Spec.
Related to this, also the size of the memory allocation is adjusted
accordingly.
Signed-off-by: Alexander Sowarka <alexander.sowarka@aerq.com>
Pali Rohár [Sat, 27 Aug 2022 14:37:55 +0000 (16:37 +0200)]
xyz-modem: Allow to configure initial timeout for loadx and loady
Now when loadx and loady commands could be aborted / cancelled by CTRL+C,
allow to configure timeout for initial x/y-modem packet via env variable
$loadxy_timeout and by default use value from new compile-time config
option CONFIG_CMD_LOADXY_TIMEOUT. Value is in seconds and zero value means
infinite timeout. Default value is 90s which is the value used before this
change for loadx command.
Other load commands loadb and loads already waits infinitely. Same behavior
for loadx and loady commands can be achieved by setting $loadxy_timeout or
CONFIG_CMD_LOADXY_TIMEOUT to 0.
This change defines resources for OP-TEE service drivers to register
themselves for being bound to when OP-TEE firmware reports the related
service is supported. OP-TEE services are discovered during optee
driver probe sequence which mandates optee driver is always probe once
bound.
Discovery of optee services and binding to related U-Boot drivers is
embedded upon configuration switch CONFIG_OPTEE_SERVICE_DISCOVERY.
Cc: Jens Wiklander <jens.wiklander@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
spl: fit: Allocate buffers aligned to cache line size
Allocate memory for buffers at a cache-line boundary to avoid
misaligned buffer address for subsequent reads. This avoids an
additional sector-based memory copy in the fat file system driver:
FAT: Misaligned buffer address (...)
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
misc: usb251xb: Support 8/16 bit device tree values
The device tree binding [1] specify the vendor-id, product-id, device-id
and language-id as 16 bit values and the linux driver reads the boost-up
value as 8 bit value.
Add functions to read 8/16-bit integers like the existing functions for
32/64-bit to simplify read of 8/16-bit integers from device tree
properties.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 14 Sep 2022 15:50:21 +0000 (11:50 -0400)]
Merge branch '2022-09-14-refactor-ramdisk-code-again' into next
To quote the author:
The previous attempt at this[1] broke a board and was reverted in [2].
This series adopts a slightly different approach, splitting the changes
into many commits.
[1] f33a2c1bd0f ("image: Remove #ifdefs from select_ramdisk()")
[2] 621158d106f ("Revert "image: Remove #ifdefs from select_ramdisk()"")
Tom Rini [Wed, 14 Sep 2022 12:57:39 +0000 (08:57 -0400)]
Merge branch '2022-09-13-add-support-for-cyclic-function-execution' into next
To quote the author:
This patchset adds the basic infrastructure to periodically execute
code, e.g. all 100ms. Examples for such functions might be LED blinking
etc. The functions that are hooked into this cyclic list should be
small timewise as otherwise the execution of the other code that relies
on a high frequent polling (e.g. UART rx char ready check) might be
delayed too much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.
How is this cyclic functionality executed?
This patchset integrates the main function responsible for calling all
registered cyclic functions cyclic_run() into the common WATCHDOG_RESET
macro. This guarantees that cyclic_run() is executed very often, which
is necessary for the cyclic functions to get scheduled and executed at
their configured periods.
This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.
Ideas how to continue:
One idea is to rename WATCHDOG_RESET to something like SCHEDULE and
move the watchdog_reset call into this cyclic infrastructure as well.
Or to perhaps move the shell UART RX ready polling to a cyclic
function.
It's also possible to extend the "cyclic" command, to support the
creation of periodically executed shell commands (for testing etc).
Masahisa Kojima [Mon, 12 Sep 2022 08:33:57 +0000 (17:33 +0900)]
doc:bootmenu: add description for UEFI boot support
The bootmenu enumerates the UEFI boot options
for boot device selection.
This commit adds the description how the UEFI boot work
in bootmenu. This commit also adds "Synopsis", "Description"
and "Configuration" sections to follow the U-Boot command
documentation format.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Masahisa Kojima [Mon, 12 Sep 2022 08:33:56 +0000 (17:33 +0900)]
eficonfig: add "Change Boot Order" menu entry
This commit adds the menu entry to update UEFI BootOrder variable.
User moves the entry with UP/DOWN key, changes the order
with PLUS/MINUS key, press SPACE to activate or deactivate
the entry, then finalizes the order by ENTER key.
If the entry is activated, the boot index is added into the
BootOrder variable in the order of the list.
The U-Boot menu framework is well designed for static menu,
this commit implements the own menu display and key handling
for dynamically change the order of menu entry.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima [Mon, 12 Sep 2022 08:33:54 +0000 (17:33 +0900)]
bootmenu: add removable media entries
UEFI specification requires booting from removal media using
a architecture-specific default image name such as BOOTAA64.EFI.
This commit adds the removable media entries into bootmenu,
so that user can select the removable media and boot with
default image.
The bootmenu automatically enumerates the possible bootable
media devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL,
add it as new UEFI boot option(BOOT####) and update BootOrder
variable. This automatically generated UEFI boot option
has the dedicated guid in the optional_data to distinguish it from
the UEFI boot option user adds manually. This optional_data is
removed when the efi bootmgr loads the selected UEFI boot option.
This commit also provides the BOOT#### variable maintenance feature.
Depending on the system hardware setup, some devices
may not exist at a later system boot, so bootmenu checks the
available device in each bootmenu invocation and automatically
removes the BOOT#### variable corrensponding to the non-existent
media device.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima [Mon, 12 Sep 2022 08:33:53 +0000 (17:33 +0900)]
eficonfig: add "Delete Boot Option" menu entry
This commit adds the menu entry to delete the UEFI boot option.
User moves the entry with UP/DOWN key, changes, then presses
ENTER key to delete the selected boot option.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima [Mon, 12 Sep 2022 08:33:51 +0000 (17:33 +0900)]
eficonfig: add "Edit Boot Option" menu entry
This commit adds the menu entry to edit the existing
BOOT#### variable contents.
User selects the item from the boot option list, then
user can edit the description, file path and optional_data.
Note that automatically generated boot option entry by bootmenu
to support the removable media device is filtered out and user
can not edit the automatically generated entry.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima [Mon, 12 Sep 2022 08:33:50 +0000 (17:33 +0900)]
eficonfig: menu-driven addition of UEFI boot option
This commit add the "eficonfig" command.
The "eficonfig" command implements the menu-driven UEFI boot option
maintenance feature. This commit implements the addition of
new boot option. User can select the block device volume having
efi_simple_file_system_protocol and select the file corresponding
to the Boot#### variable. User can also enter the description and
optional_data of the BOOT#### variable in utf8.
This commit adds "include/efi_config.h", it contains the common
definition to be used from other menus such as UEFI Secure Boot
key management.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Aaron Williams [Fri, 2 Sep 2022 11:57:52 +0000 (13:57 +0200)]
mips: octeon_nic23: Add PCIe FLR fixup via cyclic infrastructure
This patch adds a fixup function related to a PCIe FLR (Function Level
Reset) problem on the NIC23 PCIe board. This function is imported from
the Marvell Octeon 2013 U-Boot version as a (nearly) verbatim copy. It
uses the newly introduced cyclic infrastructure, so that this function
gets called every 100us, which is needed to detect this FLR issue.
Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Fri, 2 Sep 2022 11:57:51 +0000 (13:57 +0200)]
cyclic: Add 'cyclic list' and 'cyclic demo' commands
This patch adds the cyclic command, which currently only supports the
'list' subcommand, to list all currently registered cyclic functions.
Here an example:
As you can see, the cpu-time is accounted, so that cyclic functions
that take too long might be discovered. Additionally the frequency is
logged.
The 'cyclic demo' commands registers the cyclic_demo() function to
be executed all 'cycletime_ms' milliseconds. The only thing this
function does is delaying by 'delay_us' microseconds.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:50 +0000 (13:57 +0200)]
cyclic: Integrate cyclic functionality at bootup in board_r/f
This patch adds a call to cyclic_init() to board_f/r.c, enabling the
common cyclic infrastructure. After this it's possible to add cyclic
functions via cyclic_register().
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:49 +0000 (13:57 +0200)]
cyclic: Integrate cyclic infrastructure into WATCHDOG_RESET
This patch integrates the main function responsible for calling all
registered cyclic functions cyclic_run() into the common WATCHDOG_RESET
macro. This guarantees that cyclic_run() is executed very often, which
is necessary for the cyclic functions to get scheduled and executed at
their configured periods.
If CONFIG_WATCHDOG is not enabled, only cyclic_run() without calling
watchdog_reset(). This guarantees that the cyclic functionality does not
rely on CONFIG_WATCHDOG being enabled.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:48 +0000 (13:57 +0200)]
cyclic: Add basic support for cyclic function execution infrastruture
Add the basic infrastructure to periodically execute code, e.g. all
100ms. Examples for such functions might be LED blinking etc. The
functions that are hooked into this cyclic list should be small timewise
as otherwise the execution of the other code that relies on a high
frequent polling (e.g. UART rx char ready check) might be delayed too
much. This patch also adds the Kconfig option
CONFIG_CYCLIC_MAX_CPU_TIME_US, which configures the max allowed time
for such a cyclic function. If it's execution time exceeds this time,
this cyclic function will get removed from the cyclic list.
How is this cyclic functionality executed?
The following patch integrates the main function responsible for
calling all registered cyclic functions cyclic_run() into the
common WATCHDOG_RESET macro. This guarantees that cyclic_run() is
executed very often, which is necessary for the cyclic functions to
get scheduled and executed at their configured periods.
This cyclic infrastructure will be used by a board specific function on
the NIC23 MIPS Octeon board, which needs to check periodically, if a
PCIe FLR has occurred.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Stefan Roese [Fri, 2 Sep 2022 11:57:47 +0000 (13:57 +0200)]
time: Import time_after64() and friends from Linux
When using us times it makes sense to use 64bit variables for storage.
The currently implemented time_after() and friends functions only handle
32bit variables. This patch now includes the 64bit variants as well
from Linux. This will be used by the upcoming generic cyclic function
infrastructure.
These macros were copied from include/linux/jiffies.h of Linux 5.18.
Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 13 Sep 2022 19:55:33 +0000 (15:55 -0400)]
Merge branch '2022-09-13-add-aspeed-spi-controller' into next
To quote the author:
This patch series aims to porting ASPEED FMC/SPI memory controller
driver with spi-mem interface. spi-mem dirmap framework is also
synchronized from Linux. These patches have been verified on
AST2600, AST2500 and AST2400 EVBs.
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:14 +0000 (17:01 +0800)]
spi: aspeed: Clock frequency adjustment support
Driver can configure the SPI clock frequnecy to the
target value of "spi-max-frequency" property in
the device tree. The frequency is divided from HCLK,
200MHz. Usually, the ASPEED SPI clock frequency range
is between 12.5MHz and 100MHz. On AST2600, the lowest
SPI clock frequency can be about 780kHz.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:13 +0000 (17:01 +0800)]
spi: aspeed: Support customized decoded address ranges
If "decoded-ranges" is defined in the device tree, the
driver will apply the decoded address ranges from this
property to the controller during probe stage.
This patch refers to the following OpenBMC u-boot patch.
https://patchwork.ozlabs.org/project/openbmc/list/?series=306969
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:12 +0000 (17:01 +0800)]
spi: aspeed: Adjust decoded range size support
There are some known HW problems about decoded
range register configurations on existing AST2500 and
AST2600 platforms. Additional callback function,
adjust_decoded_sz, is added to solve these problems
on each platform. Besides, aspeed_spi_trim_decoded_size
function is added to modify overall decoded address
size for fitting the maximum AHB decoded size.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:10 +0000 (17:01 +0800)]
spi: aspeed: SPI dirmap read support
From the HW point of view, the performance of
command read mode is greater than user mode slightly.
Thus, dirmap read framework is introduced to achieve
this goal. In dirmap_create, command read mode is
configured. Usually, the decoded address area with flash
size is assigned to each CS. CPU can thus access the
SPI flash as normal memory in dirmap_read function.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:09 +0000 (17:01 +0800)]
mtd: spi-nor: Use spi-mem dirmap API
This adds support for the dirmap API to the spi-nor subsystem, as
introduced in Linux commit df5c21002cf4 ("mtd: spi-nor: use
spi-mem dirmap API").
This patch is synchronize from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-4-seanga2@gmail.com/
The corresponding Linux kernel SHA1 is df5c21002cf4.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:08 +0000 (17:01 +0800)]
spi-mem: Add dirmap API from Linux
This adds the dirmap API originally introduced in
Linux commit aa167f3fed0c
("spi: spi-mem: Add a new API to support direct mapping").
This also includes several follow-up patches and fixes.
Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave
This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/
The corresponding Linux kernel SHA1 is aa167f3fed0c.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Signed-off-by: Sean Anderson <seanga2@gmail.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:07 +0000 (17:01 +0800)]
arm: dts: aspeed: Update SPI flash node settings
For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:06 +0000 (17:01 +0800)]
spi: aspeed: Support AST2400 platform
Although AST2400 is EOL officially, in order to achieve
sustainability and completeness, AST2400 part is added.
For AST2400,
- Five CSs are supported by FMC controller.
- SPI1 controller only supports single CS and there is
no address segment address register. The CE control
register of SPI1 is located at the offset 0x04 and
the 4-byte address mode control bit is bit 13 of
this register.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:04 +0000 (17:01 +0800)]
spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:03 +0000 (17:01 +0800)]
pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Chin-Ting Kuo [Fri, 19 Aug 2022 09:01:02 +0000 (17:01 +0800)]
clk: aspeed: Get HCLK frequency support
User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tom Rini [Tue, 13 Sep 2022 13:34:12 +0000 (09:34 -0400)]
Merge tag 'xilinx-for-v2023.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1
cmd:
- bdinfo - guard LMB code to run only when LMB is enabled
timer:
- convert arm twd timer to DM
power-domain:
- Skip loading config object for Versal
xilinx:
- Fix logic when dfu_alt_info is generated
- Define only mmc devnum not partition
- Add xlnx prefix to GEM compatible string
- Add missing tca6416 to zynqmp SC - vck190
- Add env redund offset
- Enable CMD_GREPENV/SETEXPR by default
- Move board_get_usable_ram_top() to common location
- Add support for SOC detection
net/gem:
- Check rate before setting it up
microblaze:
- drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
- Show cache size in bdinfo
spi:
- cadence_qspi: driver updates
- zynqmp_gqspi: driver updates
- zynqmp_gqspi: Add tap delays for Versal
zynq:
- Enable mkeficapsule compilation
- Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
- Align bss and end of u-boot image to 64bits
- Align qspi node name with Linux kernel
- DT: List OCM memory
zynqmp:
- Fix AES cache handling with a user provided key
- SOM: Add mtd partition for secure OS storage area
- Add ref_clk property for REFCLKPER calculation
- Fix mdio bus description for vck190-sc
Tom Rini [Tue, 13 Sep 2022 12:59:11 +0000 (08:59 -0400)]
Merge branch '2022-09-12-update-pytests-for-more-parellel-support' into next
To quote the author:
This series makes a further attempt to get closer to having all tests
run in parallel. It introduces a new 'make pcheck' option which runs
tests in parallel, skipping those that are not compatible.
A number of fixes are included for existing tests. The vboot test is
updated to only run a single scenario in 'quick' mode.
This makes use of pytest's parallel-testing features. The resulting
times (including incremental building with LTO) on a 16-core machine are
as follows:
make pcheck - 1 minute 6 seconds
make qcheck - 3 minutes
make check - 5 minutes 15 seconds
Note that this is not a fair comparison, since 'make pcheck' omits a
number of tests, even more than 'make qcheck'.
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