From: Tom Rini Date: Mon, 13 Nov 2023 14:07:23 +0000 (-0500) Subject: Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot... X-Git-Url: http://git.dujemihanovic.xyz/html/index.html?a=commitdiff_plain;h=be0724601a9dd6aebca04337b1299edd126bbb4e;p=u-boot.git Merge tag 'u-boot-stm32-20231113' of https://source.denx.de/u-boot/custodians/u-boot-stm into next Introduce STM32MP2 SoCs family support Add STM32MP257F-EV1 board [trini: Adjust some includes] Signed-off-by: Tom Rini --- be0724601a9dd6aebca04337b1299edd126bbb4e diff --cc arch/arm/mach-stm32mp/include/mach/stm32.h index 1cdc5e3b18,ce9d795651..b31e4a5d0d --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@@ -6,8 -6,60 +6,61 @@@ #ifndef _MACH_STM32_H_ #define _MACH_STM32_H_ ++#include #ifndef __ASSEMBLY__ #include + + enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, + }; + + #define TAMP_BOOT_MODE_MASK GENMASK(15, 8) + #define TAMP_BOOT_MODE_SHIFT 8 + #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) + #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) + #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) + #define TAMP_BOOT_DEBUG_ON BIT(16) + + enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, + }; + #endif /* diff --cc arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c index 0000000000,a203eebdc5..36c631ef0c mode 000000,100644..100644 --- a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@@ -1,0 -1,68 +1,68 @@@ + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + /* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + -#include + #include + #include ++#include + + #define MP2_MEM_MAP_MAX 10 + + #if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) + #error "invalid CONFIG_TEXT_BASE value" + #endif + + struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } + }; + + struct mm_region *mem_map = stm32mp2_mem_map; diff --cc arch/arm/mach-stm32mp/stm32mp2/cpu.c index 0000000000,5bfeab17ab..f43d1aaf72 mode 000000,100644..100644 --- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@@ -1,0 -1,108 +1,107 @@@ + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + /* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + + #define LOG_CATEGORY LOGC_ARCH + -#include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ + #define EARLY_TLB_SIZE 0xA000 + u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + + /* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ + static void early_enable_caches(void) + { + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); + } + + /* + * Early system init + */ + int arch_cpu_init(void) + { + icache_enable(); + early_enable_caches(); + + return 0; + } + + void enable_caches(void) + { + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); + } + + /* used when CONFIG_DISPLAY_CPUINFO is activated */ + int print_cpuinfo(void) + { + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; + } + + int arch_misc_init(void) + { + return 0; + } + + /* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ + static uintptr_t nt_fw_dtb __section(".data"); + + uintptr_t get_stm32mp_bl2_dtb(void) + { + return nt_fw_dtb; + } + + /* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ + void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) + { + nt_fw_dtb = r2; + + save_boot_params_ret(); + } diff --cc arch/arm/mach-stm32mp/stm32mp2/fdt.c index 0000000000,ee570863bb..31b127b465 mode 000000,100644..100644 --- a/arch/arm/mach-stm32mp/stm32mp2/fdt.c +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@@ -1,0 -1,16 +1,16 @@@ + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + /* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + -#include ++#include + + /* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ + int ft_system_setup(void *blob, struct bd_info *bd) + { + return 0; + } + diff --cc arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c index 0000000000,7d2dab2201..4b2f70af9c mode 000000,100644..100644 --- a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@@ -1,0 -1,194 +1,193 @@@ + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + /* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + + #define LOG_CATEGORY LOGC_ARCH + -#include + #include + #include + #include + #include + #include + + /* SYSCFG register */ + #define SYSCFG_DEVICEID_OFFSET 0x6400 + #define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) + #define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 + #define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) + #define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + + /* Device Part Number (RPN) = OTP9 */ + #define RPN_SHIFT 0 + #define RPN_MASK GENMASK(31, 0) + + /* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ + #define PKG_SHIFT 0 + #define PKG_MASK GENMASK(2, 0) + + static u32 read_deviceid(void) + { + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); + } + + u32 get_cpu_dev(void) + { + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; + } + + u32 get_cpu_rev(void) + { + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; + } + + /* Get Device Part Number (RPN) from OTP */ + u32 get_cpu_type(void) + { + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); + } + + /* Get Package options from OTP */ + u32 get_cpu_package(void) + { + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); + } + + int get_eth_nb(void) + { + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; + } + + void get_soc_name(char name[SOC_NAME_SIZE]) + { + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); + } diff --cc board/st/stm32mp2/stm32mp2.c index 0000000000,132c511ce9..c97a7efff4 mode 000000,100644..100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@@ -1,0 -1,52 +1,51 @@@ + // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause + /* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + + #define LOG_CATEGORY LOGC_BOARD + -#include + #include + #include + #include + #include + #include + + /* + * Get a global data pointer + */ + DECLARE_GLOBAL_DATA_PTR; + + /* board dependent setup after realloc */ + int board_init(void) + { + return 0; + } + + int board_late_init(void) + { + const void *fdt_compat; + int fdt_compat_len; + char dtb_name[256]; + int buf_len; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) { + env_set("board_name", fdt_compat); + } else { + env_set("board_name", fdt_compat + 3); + + buf_len = sizeof(dtb_name); + strlcpy(dtb_name, fdt_compat + 3, buf_len); + buf_len -= strlen(fdt_compat + 3); + strlcat(dtb_name, ".dtb", buf_len); + env_set("fdtfile", dtb_name); + } + } + } + + return 0; + }