From: Alban Bedel Date: Wed, 20 Nov 2013 16:42:46 +0000 (+0100) Subject: arm: tegra: Fix the CPU complex reset masks X-Git-Tag: v2025.01-rc5-pxa1908~15542^2 X-Git-Url: http://git.dujemihanovic.xyz/html/index.html?a=commitdiff_plain;h=766afc3dff35f8f257deb0373735a328c8206880;p=u-boot.git arm: tegra: Fix the CPU complex reset masks The CPU complex reset masks are not matching with the datasheet for the CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 registers. For both T20 and T30 the register consist of groups of 4 bits, with one bit for each CPU core. On T20 the 2 high bits of each group are always stubbed as there is only 2 cores. Signed-off-by: Alban Bedel Acked-by: Stephen Warren Tested-by: Stephen Warren Signed-off-by: Tom Warren --- diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index c3174bd7fc..e7d0fd45ee 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable); enum crc_reset_id { /* Things we can hold in reset for each CPU */ crc_rst_cpu = 1, - crc_rst_de = 1 << 2, /* What is de? */ - crc_rst_watchdog = 1 << 3, - crc_rst_debug = 1 << 4, + crc_rst_de = 1 << 4, /* What is de? */ + crc_rst_watchdog = 1 << 8, + crc_rst_debug = 1 << 12, }; /**