From: Samuel Holland <samuel@sholland.org>
Date: Tue, 31 Oct 2023 05:35:41 +0000 (-0500)
Subject: riscv: Align the trap handler to 64 bytes
X-Git-Url: http://git.dujemihanovic.xyz/html/index.html?a=commitdiff_plain;h=3b00fab616b1150da745bbb36f6644842a24624f;p=u-boot.git

riscv: Align the trap handler to 64 bytes

This is required on CPUs which always operate in CLIC mode, such as the
T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
trap vector base address held in mtvec is constrained to be aligned on a
64-byte or larger power-of-two boundary."

Reported-by: Madushan Nishantha <jlmadushan@gmail.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
index 6eb3ed1d5a..5cad7b41ff 100644
--- a/arch/riscv/cpu/mtrap.S
+++ b/arch/riscv/cpu/mtrap.S
@@ -26,7 +26,7 @@
 	.text
 
 	/* trap entry */
-	.align 2
+	.align 6
 	.global trap_entry
 trap_entry:
 	addi sp, sp, -32 * REGBYTES