From: Chris Packham Date: Thu, 28 Feb 2019 21:11:14 +0000 (+1300) Subject: mv_ddr: ddr3: only use active chip-selects when tuning ODT X-Git-Url: http://git.dujemihanovic.xyz/html/index.html?a=commitdiff_plain;h=247c80d6b8ad07871845a846796ae6b40f34b4f6;p=u-boot.git mv_ddr: ddr3: only use active chip-selects when tuning ODT Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham Signed-off-by: Stefan Roese --- diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index db0f8ad7fb..df832ac6dc 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -50,6 +50,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) int max_phase = MIN_VALUE, current_phase; enum hws_access_type access_type = ACCESS_TYPE_UNICAST; u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); + unsigned int max_cs = mv_ddr_cs_num_get(); CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, @@ -59,7 +60,7 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) data_read, MASK_ALL_BITS)); val = data_read[if_id]; - for (cs_num = 0; cs_num < MAX_CS_NUM; cs_num++) { + for (cs_num = 0; cs_num < max_cs; cs_num++) { read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num); /* find maximum of read_samples */