si->clk_bus = gd->bus_clk;
si->clk_cpu = gd->cpu_clk;
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
#define bi_bar bi_immr_base
#elif defined(CONFIG_MPC83xx)
#define bi_bar bi_immrbar
select SYS_FSL_DDR_BE
imply CMD_REGINFO
-config 8xx
+config MPC8xx
bool "MPC8xx"
imply CMD_REGINFO
menu "mpc8xx CPU"
- depends on 8xx
+ depends on MPC8xx
config SYS_CPU
default "mpc8xx"
#include <common.h>
#include <command.h>
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
#include <commproc.h>
#include <asm/iopin_8xx.h>
#include <asm/io.h>
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
-#ifdef CONFIG_8xx
+#ifdef CONFIG_MPC8xx
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
mtspr(DC_ADR, val);
}
#endif
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
#endif
u8 sdhc_adapter;
#endif
#endif
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
unsigned long brg_clk;
#endif
#if defined(CONFIG_CPM2)
#define _ASM_IOPIN_8XX_H_
#include <linux/types.h>
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
#include <asm/io.h>
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
-#if defined(CONFIG_8xx)
-#include <asm/8xx_immap.h>
+#if defined(CONFIG_MPC8xx)
+#include <asm/immap_8xx.h>
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
print_bi_flash(bd);
print_num("sramstart", bd->bi_sramstart);
print_num("sramsize", bd->bi_sramsize);
-#if defined(CONFIG_8xx) || defined(CONFIG_E500)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
print_num("immr_base", bd->bi_immr_base);
#endif
print_num("bootflags", bd->bi_bootflags);
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x4000000
-CONFIG_8xx=y
+CONFIG_MPC8xx=y
CONFIG_TARGET_MCR3000=y
CONFIG_8xx_GCLK_FREQ=132000000
CONFIG_CMD_IMMAP=y
config MPC8XX_FEC
bool "Fast Ethernet Controller on MPC8XX"
- depends on 8xx
+ depends on MPC8xx
select MII
help
This driver implements support for the Fast Ethernet Controller
config MPC8XX_CONS
bool "Console driver for MPC8XX"
- depends on 8xx
+ depends on MPC8xx
default y
choice
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
- depends on 8xx
+ depends on MPC8xx
help
Enable support for SPI on MPC8XX
unsigned long bi_dsp_freq; /* dsp core frequency */
unsigned long bi_ddr_freq; /* ddr frequency */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_M68K)
#ifndef __CPM_8XX__
#define __CPM_8XX__
-#include <asm/8xx_immap.h>
+#include <asm/immap_8xx.h>
/* CPM Command register.
*/
#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
-#if 0 /* already in asm/8xx_immap.h */
+#if 0 /* already in asm/immap_8xx.h */
#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
*/
#undef PISCR_PIRQ /* TBD */
#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
-#if 0 /* already in asm/8xx_immap.h */
+#if 0 /* already in asm/immap_8xx.h */
#define PISCR_PS 0x0080 /* Periodic interrupt Status */
#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
#define r30 30
#define r31 31
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
/* Some special registers */
#define LCTRL2 157 /* Load/Store Support (37-41) */
#define ICTRL 158
-#endif /* CONFIG_8xx */
+#endif /* CONFIG_MPC8xx */
-#if defined(CONFIG_8xx)
+#if defined(CONFIG_MPC8xx)
/* Registers in the processor's internal memory map that we use.
*/
*/
/* MPC 8xx */
-#if defined(CONFIG_8xx) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_MPC8xx) && !defined(__ASSEMBLY__)
void reset_8xx_watchdog(immap_t __iomem *immr);
#endif