]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: ventana: add support for GW5908
authorTim Harvey <tharvey@gateworks.com>
Mon, 4 Feb 2019 21:10:56 +0000 (13:10 -0800)
committerStefano Babic <sbabic@denx.de>
Fri, 15 Feb 2019 21:01:15 +0000 (22:01 +0100)
The GW5908 is a small single board computer based on the i.MX6DL SoC
with the same peripheral set as the GW530x but with 1GiB density DRAM
(64bit 512MiB).

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
board/gateworks/gw_ventana/common.c
board/gateworks/gw_ventana/eeprom.c
board/gateworks/gw_ventana/gw_ventana_spl.c
board/gateworks/gw_ventana/ventana_eeprom.h

index 2b0bf0e7cc6ca55ec4bc1408b273fb39db15a2e3..568dc920ae784da630b8bc14ac57feed5af203c2 100644 (file)
@@ -1112,6 +1112,27 @@ struct ventana gpio_cfg[GW_UNKNOWN] = {
                .wdis = IMX_GPIO_NR(7, 12),
                .nand = true,
        },
+
+       /* GW5908 */
+       {
+               .gpio_pads = gw53xx_gpio_pads,
+               .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
+               .dio_cfg = gw53xx_dio,
+               .dio_num = ARRAY_SIZE(gw53xx_dio),
+               .leds = {
+                       IMX_GPIO_NR(4, 6),
+                       IMX_GPIO_NR(4, 7),
+                       IMX_GPIO_NR(4, 15),
+               },
+               .pcie_rst = IMX_GPIO_NR(1, 29),
+               .mezz_pwren = IMX_GPIO_NR(2, 19),
+               .mezz_irq = IMX_GPIO_NR(2, 18),
+               .gps_shdn = IMX_GPIO_NR(1, 27),
+               .vidin_en = IMX_GPIO_NR(3, 31),
+               .wdis = IMX_GPIO_NR(7, 12),
+               .msata_en = GP_MSATA_SEL,
+               .rs232_en = GP_RS232_EN,
+       },
 };
 
 #define SETUP_GPIO_OUTPUT(gpio, name, level) \
index 3aaf195b65b5ff9a13232938a0fd717be84bae6f..85802141dd5251b62dad1a881d5c39c9f3d865ae 100644 (file)
@@ -107,6 +107,8 @@ read_eeprom(int bus, struct ventana_board_info *info)
                        type = GW5906;
                else if (info->model[4] == '0' && info->model[5] == '7')
                        type = GW5907;
+               else if (info->model[4] == '0' && info->model[5] == '8')
+                       type = GW5908;
                break;
        }
        return type;
index 280493dd46943844775dc5836651da82fc2bcb94..27f3774140e538fb55108dba49cbe63ee339c5b3 100644 (file)
@@ -217,6 +217,46 @@ static struct mx6_mmdc_calibration mx6sdl_64x16_mmdc_calib = {
        .p0_mpwrdlctl = 0x33382C31,
 };
 
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6dq_64x64_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x00190017,
+       .p0_mpwldectrl1 = 0x00140026,
+       .p1_mpwldectrl0 = 0x0021001C,
+       .p1_mpwldectrl1 = 0x0011001D,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x43380347,
+       .p0_mpdgctrl1 = 0x433C034D,
+       .p1_mpdgctrl0 = 0x032C0324,
+       .p1_mpdgctrl1 = 0x03310232,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x3C313539,
+       .p1_mprddlctl = 0x37343141,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x36393C39,
+       .p1_mpwrdlctl = 0x42344438,
+};
+
+/* TODO: update with calibrated values */
+static struct mx6_mmdc_calibration mx6sdl_64x64_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x003C003C,
+       .p0_mpwldectrl1 = 0x001F002A,
+       .p1_mpwldectrl0 = 0x00330038,
+       .p1_mpwldectrl1 = 0x0022003F,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x42410244,
+       .p0_mpdgctrl1 = 0x4234023A,
+       .p1_mpdgctrl0 = 0x022D022D,
+       .p1_mpdgctrl1 = 0x021C0228,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x484A4C4B,
+       .p1_mprddlctl = 0x4B4D4E4B,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x33342B32,
+       .p1_mpwrdlctl = 0x3933332B,
+};
+
 static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = {
        /* write leveling calibration determine */
        .p0_mpwldectrl0 = 0x001B0016,
@@ -530,6 +570,10 @@ static void spl_dram_init(int width, int size_mb, int board_model)
        } else if (width == 64 && size_mb == 512) {
                mem = &mt41k64m16jt_125;
                debug("1gB density\n");
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_64x64_mmdc_calib;
+               else
+                       calib = &mx6sdl_64x64_mmdc_calib;
        } else if (width == 64 && size_mb == 1024) {
                mem = &mt41k128m16jt_125;
                if (is_cpu_type(MXC_CPU_MX6Q))
index c6a38f121800c5b9593452d325d409dbbdaabc5e..c80dfa1f7a3fb269113a3025df4971ac9f3ca9af 100644 (file)
@@ -117,6 +117,7 @@ enum {
        GW5905,
        GW5906,
        GW5907,
+       GW5908,
        GW_UNKNOWN,
        GW_BADCRC,
 };