fpga: xilinx: add bitstream flags to driver desc

Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 69b818f24b890c00b3cf6f800d3e08b71425ec19..ac595ee0a27118b4d85db008be1da825fee10b1e 100644 (file)
--- a/arch/arm/mach-zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
@@ -22,6 +22,7 @@ xilinx_desc fpga = {
        .family = xilinx_zynq,
        .iface = devcfg,
        .operations = &zynq_op,
+       .flags = FPGA_LEGACY,
 };
 #endif
 

diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 81663e0cd0ed14d123c84429dc053b6729ce2645..d8f39be56c873aefb5571425329862e6c04b7604 100644 (file)
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -27,7 +27,10 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_FPGA_VERSALPL)
-static xilinx_desc versalpl = XILINX_VERSAL_DESC;
+static xilinx_desc versalpl = {
+       xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
+       FPGA_LEGACY
+};
 #endif
 
 int board_init(void)

diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index f7c6e3ed4e3f6a3ac3353f2a86f96b14837bf7de..57259b60a02eaaea6f97f299aaa82287928fb6f7 100644 (file)
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -48,7 +48,10 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
-static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
+static xilinx_desc zynqmppl = {
+       xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op, NULL,
+       ZYNQMP_FPGA_FLAGS
+};
 #endif
 
 int __maybe_unused psu_uboot_init(void)

diff --git a/include/versalpl.h b/include/versalpl.h
index b94c82e6e666d7d6d32e730866b481be2eb5423e..0cc101be2f84cd14b8d719fc3f273fffcf1c39ec 100644 (file)
--- a/include/versalpl.h
+++ b/include/versalpl.h
@@ -14,7 +14,4 @@
 
 extern struct xilinx_fpga_op versal_op;
 
-#define XILINX_VERSAL_DESC \
-{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
-
 #endif /* _VERSALPL_H_ */

diff --git a/include/xilinx.h b/include/xilinx.h
index 362943bc717db35d8ae696d0b9ac56f0c4df64db..d9e4b8da96871bdb81ba19b3499ee1b998e30ec8 100644 (file)
--- a/include/xilinx.h
+++ b/include/xilinx.h
@@ -37,6 +37,9 @@ typedef enum {                        /* typedef xilinx_family */
        max_xilinx_type         /* insert all new types before this */
 } xilinx_family;               /* end, typedef xilinx_family */
 
+/* FPGA bitstream supported types */
+#define FPGA_LEGACY                    BIT(0)
+
 typedef struct {               /* typedef xilinx_desc */
        xilinx_family family;   /* part type */
        xilinx_iface iface;     /* interface type */
@@ -45,6 +48,7 @@ typedef struct {              /* typedef xilinx_desc */
        int cookie;             /* implementation specific cookie */
        struct xilinx_fpga_op *operations; /* operations */
        char *name;             /* device name in bitstream */
+       int flags;              /* compatible flags */
 } xilinx_desc;                 /* end, typedef xilinx_desc */
 
 struct xilinx_fpga_op {

diff --git a/include/zynqmppl.h b/include/zynqmppl.h
index 35cfe17d44414f2bc451d07ea2a49362f5d6e2ff..8401a850afb29ad507595d596e5f32e7169b49dd 100644 (file)
--- a/include/zynqmppl.h
+++ b/include/zynqmppl.h
@@ -25,7 +25,6 @@
 
 extern struct xilinx_fpga_op zynqmp_op;
 
-#define XILINX_ZYNQMP_DESC \
-{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
+#define ZYNQMP_FPGA_FLAGS      (FPGA_LEGACY)
 
 #endif /* _ZYNQMPPL_H_ */