Enable BATs (block address translation registers) 4-7 on machines
that support them.
+config SYS_INIT_RAM_LOCK
+ bool "Lock some portion of L1 for initial ram stack"
+ depends on MPC83xx || MPC85xx
+
source "arch/powerpc/cpu/mpc83xx/Kconfig"
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
extern void flush_dcache(void);
extern void invalidate_dcache(void);
extern void invalidate_icache(void);
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
-#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_MPC837XERDB=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_5_1=y
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
CONFIG_ENV_ADDR=0xFFF60000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_MPC8548CDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PA=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P1010RDB_PB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_MPC85XX_NO_RESETVEC=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PC=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020RDB_PD=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_SPL=y
CONFIG_TPL_MAX_SIZE=0x20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P2020RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENV_OFFSET=0xE0000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_ENV_OFFSET=0xCF400
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1024RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T1042D4RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xFFE20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t2080rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T2080RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T4240RDB=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_BOOK3E_HV=y
CONFIG_DEFAULT_DEVICE_TREE="t4240rdb"
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_T4240RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_ENV_ADDR=0xFE080000
CONFIG_MPC83xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_GAZERBEAM=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_ENV_ADDR=0xebf20000
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMCENT2=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMCOGE5NE=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_VCO_DIV_4=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMETER1=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_VCO_DIV_4=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMOPTI2=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMSUPX5=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_KMTEPR2=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
CONFIG_ENV_ADDR=0xFFF40000
# CONFIG_SYS_PCI_64BIT is not set
CONFIG_MPC85xx=y
+CONFIG_SYS_INIT_RAM_LOCK=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_SOCRATES=y
CONFIG_ENABLE_36BIT_PHYS=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUGE1=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
+CONFIG_SYS_INIT_RAM_LOCK=y
CONFIG_TARGET_TUXX1=y
CONFIG_CORE_PLL_RATIO_25_1=y
CONFIG_QUICC_MULT_FACTOR_3=y
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
/*
* Initial RAM Base Address Setup
*/
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
/*
#define CONFIG_HWCONFIG
/* define to use L1 as initial stack */
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/